Home
last modified time | relevance | path

Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT (Results 1 – 9 of 9) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h1866 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 macro
Dgfx_8_1_sh_mask.h2388 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11188 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
Dgc_9_1_sh_mask.h12669 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
Dgc_9_2_1_sh_mask.h12467 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
Dgc_9_4_2_sh_mask.h2576 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
Dgc_11_0_0_sh_mask.h15600 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
Dgc_10_1_0_sh_mask.h18147 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
Dgc_10_3_0_sh_mask.h16498 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro