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Searched refs:CPLL (Results 1 – 3 of 3) sorted by relevance

/linux-5.19.10/arch/arm/boot/dts/
Dexynos5422-odroid-core.dtsi67 /* derived from 666MHz CPLL */
85 /* derived from 666MHz CPLL */
112 /* derived from 666MHz CPLL */
151 /* derived from 666MHz CPLL */
160 /* derived from 666MHz CPLL */
217 /* derived from 666MHz CPLL */
277 /* derived from 666MHz CPLL */
/linux-5.19.10/include/dt-bindings/clock/
Dxlnx-versal-clk.h35 #define CPLL 26 macro
/linux-5.19.10/arch/arm64/boot/dts/rockchip/
Drk3328.dtsi784 * CPLL should run at 1200, but that is to high for