1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RoCE HSI File - Autogenerated 37 */ 38 39 #ifndef __BNXT_RE_HSI_H__ 40 #define __BNXT_RE_HSI_H__ 41 42 /* include bnxt_hsi.h from bnxt_en driver */ 43 #include "bnxt_hsi.h" 44 45 /* CMP Door Bell Format (4 bytes) */ 46 struct cmpl_doorbell { 47 __le32 key_mask_valid_idx; 48 #define CMPL_DOORBELL_IDX_MASK 0xffffffUL 49 #define CMPL_DOORBELL_IDX_SFT 0 50 #define CMPL_DOORBELL_RESERVED_MASK 0x3000000UL 51 #define CMPL_DOORBELL_RESERVED_SFT 24 52 #define CMPL_DOORBELL_IDX_VALID 0x4000000UL 53 #define CMPL_DOORBELL_MASK 0x8000000UL 54 #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL 55 #define CMPL_DOORBELL_KEY_SFT 28 56 #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28) 57 }; 58 59 /* Status Door Bell Format (4 bytes) */ 60 struct status_doorbell { 61 __le32 key_idx; 62 #define STATUS_DOORBELL_IDX_MASK 0xffffffUL 63 #define STATUS_DOORBELL_IDX_SFT 0 64 #define STATUS_DOORBELL_RESERVED_MASK 0xf000000UL 65 #define STATUS_DOORBELL_RESERVED_SFT 24 66 #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL 67 #define STATUS_DOORBELL_KEY_SFT 28 68 #define STATUS_DOORBELL_KEY_STAT (0x3UL << 28) 69 }; 70 71 /* RoCE Host Structures */ 72 73 /* Doorbell Structures */ 74 /* dbc_dbc (size:64b/8B) */ 75 struct dbc_dbc { 76 __le32 index; 77 #define DBC_DBC_INDEX_MASK 0xffffffUL 78 #define DBC_DBC_INDEX_SFT 0 79 __le32 type_path_xid; 80 #define DBC_DBC_XID_MASK 0xfffffUL 81 #define DBC_DBC_XID_SFT 0 82 #define DBC_DBC_PATH_MASK 0x3000000UL 83 #define DBC_DBC_PATH_SFT 24 84 #define DBC_DBC_PATH_ROCE (0x0UL << 24) 85 #define DBC_DBC_PATH_L2 (0x1UL << 24) 86 #define DBC_DBC_PATH_ENGINE (0x2UL << 24) 87 #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE 88 #define DBC_DBC_DEBUG_TRACE 0x8000000UL 89 #define DBC_DBC_TYPE_MASK 0xf0000000UL 90 #define DBC_DBC_TYPE_SFT 28 91 #define DBC_DBC_TYPE_SQ (0x0UL << 28) 92 #define DBC_DBC_TYPE_RQ (0x1UL << 28) 93 #define DBC_DBC_TYPE_SRQ (0x2UL << 28) 94 #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28) 95 #define DBC_DBC_TYPE_CQ (0x4UL << 28) 96 #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28) 97 #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28) 98 #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28) 99 #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28) 100 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28) 101 #define DBC_DBC_TYPE_NQ (0xaUL << 28) 102 #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28) 103 #define DBC_DBC_TYPE_NULL (0xfUL << 28) 104 #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL 105 }; 106 107 /* dbc_dbc32 (size:32b/4B) */ 108 struct dbc_dbc32 { 109 __le32 type_abs_incr_xid; 110 #define DBC_DBC32_XID_MASK 0xfffffUL 111 #define DBC_DBC32_XID_SFT 0 112 #define DBC_DBC32_PATH_MASK 0xc00000UL 113 #define DBC_DBC32_PATH_SFT 22 114 #define DBC_DBC32_PATH_ROCE (0x0UL << 22) 115 #define DBC_DBC32_PATH_L2 (0x1UL << 22) 116 #define DBC_DBC32_PATH_LAST DBC_DBC32_PATH_L2 117 #define DBC_DBC32_INCR_MASK 0xf000000UL 118 #define DBC_DBC32_INCR_SFT 24 119 #define DBC_DBC32_ABS 0x10000000UL 120 #define DBC_DBC32_TYPE_MASK 0xe0000000UL 121 #define DBC_DBC32_TYPE_SFT 29 122 #define DBC_DBC32_TYPE_SQ (0x0UL << 29) 123 #define DBC_DBC32_TYPE_LAST DBC_DBC32_TYPE_SQ 124 }; 125 126 /* SQ WQE Structures */ 127 /* Base SQ WQE (8 bytes) */ 128 struct sq_base { 129 u8 wqe_type; 130 #define SQ_BASE_WQE_TYPE_SEND 0x0UL 131 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL 132 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL 133 #define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL 134 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 135 #define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL 136 #define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL 137 #define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL 138 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL 139 #define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL 140 #define SQ_BASE_WQE_TYPE_BIND 0xeUL 141 u8 unused_0[7]; 142 }; 143 144 /* WQE SGE (16 bytes) */ 145 struct sq_sge { 146 __le64 va_or_pa; 147 __le32 l_key; 148 __le32 size; 149 }; 150 151 /* PSN Search Structure (8 bytes) */ 152 struct sq_psn_search { 153 __le32 opcode_start_psn; 154 #define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL 155 #define SQ_PSN_SEARCH_START_PSN_SFT 0 156 #define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL 157 #define SQ_PSN_SEARCH_OPCODE_SFT 24 158 __le32 flags_next_psn; 159 #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL 160 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0 161 #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL 162 #define SQ_PSN_SEARCH_FLAGS_SFT 24 163 }; 164 165 /* sq_psn_search_ext (size:128b/16B) */ 166 struct sq_psn_search_ext { 167 __le32 opcode_start_psn; 168 #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL 169 #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0 170 #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL 171 #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24 172 __le32 flags_next_psn; 173 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL 174 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0 175 #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL 176 #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24 177 __le16 start_slot_idx; 178 __le16 reserved16; 179 __le32 reserved32; 180 }; 181 182 /* Send SQ WQE (40 bytes) */ 183 struct sq_send { 184 u8 wqe_type; 185 #define SQ_SEND_WQE_TYPE_SEND 0x0UL 186 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL 187 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL 188 u8 flags; 189 #define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL 190 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 191 #define SQ_SEND_FLAGS_UC_FENCE 0x4UL 192 #define SQ_SEND_FLAGS_SE 0x8UL 193 #define SQ_SEND_FLAGS_INLINE 0x10UL 194 u8 wqe_size; 195 u8 reserved8_1; 196 __le32 inv_key_or_imm_data; 197 __le32 length; 198 __le32 q_key; 199 __le32 dst_qp; 200 #define SQ_SEND_DST_QP_MASK 0xffffffUL 201 #define SQ_SEND_DST_QP_SFT 0 202 #define SQ_SEND_RESERVED8_2_MASK 0xff000000UL 203 #define SQ_SEND_RESERVED8_2_SFT 24 204 __le32 avid; 205 #define SQ_SEND_AVID_MASK 0xfffffUL 206 #define SQ_SEND_AVID_SFT 0 207 #define SQ_SEND_RESERVED_AVID_MASK 0xfff00000UL 208 #define SQ_SEND_RESERVED_AVID_SFT 20 209 __le64 reserved64; 210 __le32 data[24]; 211 }; 212 213 /* sq_send_hdr (size:256b/32B) */ 214 struct sq_send_hdr { 215 u8 wqe_type; 216 u8 flags; 217 u8 wqe_size; 218 u8 reserved8_1; 219 __le32 inv_key_or_imm_data; 220 __le32 length; 221 __le32 q_key; 222 __le32 dst_qp; 223 __le32 avid; 224 __le64 reserved64; 225 }; 226 227 /* Send Raw Ethernet and QP1 SQ WQE (40 bytes) */ 228 struct sq_send_raweth_qp1 { 229 u8 wqe_type; 230 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL 231 u8 flags; 232 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL 233 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 234 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL 235 #define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL 236 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL 237 u8 wqe_size; 238 u8 reserved8; 239 __le16 lflags; 240 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL 241 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL 242 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL 243 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL 244 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL 245 #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_1 0x20UL 246 #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_2 0x40UL 247 #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_3 0x80UL 248 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL 249 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL 250 __le16 cfa_action; 251 __le32 length; 252 __le32 reserved32_1; 253 __le32 cfa_meta; 254 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL 255 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0 256 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL 257 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL 258 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13 259 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL 260 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16 261 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 262 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 263 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 264 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 265 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 266 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 267 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST \ 268 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG 269 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 270 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19 271 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL 272 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28 273 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28) 274 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 275 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST \ 276 SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG 277 __le32 reserved32_2; 278 __le64 reserved64; 279 __le32 data[24]; 280 }; 281 282 /* sq_send_raweth_qp1_hdr (size:256b/32B) */ 283 struct sq_send_raweth_qp1_hdr { 284 u8 wqe_type; 285 u8 flags; 286 u8 wqe_size; 287 u8 reserved8; 288 __le16 lflags; 289 __le16 cfa_action; 290 __le32 length; 291 __le32 reserved32_1; 292 __le32 cfa_meta; 293 __le32 reserved32_2; 294 __le64 reserved64; 295 }; 296 297 /* RDMA SQ WQE (40 bytes) */ 298 struct sq_rdma { 299 u8 wqe_type; 300 #define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL 301 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 302 #define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL 303 u8 flags; 304 #define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL 305 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 306 #define SQ_RDMA_FLAGS_UC_FENCE 0x4UL 307 #define SQ_RDMA_FLAGS_SE 0x8UL 308 #define SQ_RDMA_FLAGS_INLINE 0x10UL 309 u8 wqe_size; 310 u8 reserved8; 311 __le32 imm_data; 312 __le32 length; 313 __le32 reserved32_1; 314 __le64 remote_va; 315 __le32 remote_key; 316 __le32 reserved32_2; 317 __le32 data[24]; 318 }; 319 320 /* sq_rdma_hdr (size:256b/32B) */ 321 struct sq_rdma_hdr { 322 u8 wqe_type; 323 u8 flags; 324 u8 wqe_size; 325 u8 reserved8; 326 __le32 imm_data; 327 __le32 length; 328 __le32 reserved32_1; 329 __le64 remote_va; 330 __le32 remote_key; 331 __le32 reserved32_2; 332 }; 333 334 /* Atomic SQ WQE (40 bytes) */ 335 struct sq_atomic { 336 u8 wqe_type; 337 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL 338 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL 339 u8 flags; 340 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL 341 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 342 #define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL 343 #define SQ_ATOMIC_FLAGS_SE 0x8UL 344 #define SQ_ATOMIC_FLAGS_INLINE 0x10UL 345 __le16 reserved16; 346 __le32 remote_key; 347 __le64 remote_va; 348 __le64 swap_data; 349 __le64 cmp_data; 350 __le32 data[24]; 351 }; 352 353 /* sq_atomic_hdr (size:256b/32B) */ 354 struct sq_atomic_hdr { 355 u8 wqe_type; 356 u8 flags; 357 __le16 reserved16; 358 __le32 remote_key; 359 __le64 remote_va; 360 __le64 swap_data; 361 __le64 cmp_data; 362 }; 363 364 /* Local Invalidate SQ WQE (40 bytes) */ 365 struct sq_localinvalidate { 366 u8 wqe_type; 367 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL 368 u8 flags; 369 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL 370 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 371 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL 372 #define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL 373 #define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL 374 __le16 reserved16; 375 __le32 inv_l_key; 376 __le64 reserved64; 377 __le32 reserved128[4]; 378 __le32 data[24]; 379 }; 380 381 /* sq_localinvalidate_hdr (size:256b/32B) */ 382 struct sq_localinvalidate_hdr { 383 u8 wqe_type; 384 u8 flags; 385 __le16 reserved16; 386 __le32 inv_l_key; 387 __le64 reserved64; 388 u8 reserved128[16]; 389 }; 390 391 /* FR-PMR SQ WQE (40 bytes) */ 392 struct sq_fr_pmr { 393 u8 wqe_type; 394 #define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL 395 u8 flags; 396 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL 397 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 398 #define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL 399 #define SQ_FR_PMR_FLAGS_SE 0x8UL 400 #define SQ_FR_PMR_FLAGS_INLINE 0x10UL 401 u8 access_cntl; 402 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 403 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL 404 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 405 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 406 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL 407 u8 zero_based_page_size_log; 408 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL 409 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0 410 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 411 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 412 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 413 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 414 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 415 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 416 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 417 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 418 #define SQ_FR_PMR_ZERO_BASED 0x20UL 419 #define SQ_FR_PMR_RESERVED2_MASK 0xc0UL 420 #define SQ_FR_PMR_RESERVED2_SFT 6 421 __le32 l_key; 422 u8 length[5]; 423 u8 reserved8_1; 424 u8 reserved8_2; 425 u8 numlevels_pbl_page_size_log; 426 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 427 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0 428 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 429 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 430 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 431 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 432 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 433 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 434 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 435 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 436 #define SQ_FR_PMR_RESERVED1 0x20UL 437 #define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL 438 #define SQ_FR_PMR_NUMLEVELS_SFT 6 439 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6) 440 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6) 441 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6) 442 __le64 pblptr; 443 __le64 va; 444 __le32 data[24]; 445 }; 446 447 /* sq_fr_pmr_hdr (size:256b/32B) */ 448 struct sq_fr_pmr_hdr { 449 u8 wqe_type; 450 u8 flags; 451 u8 access_cntl; 452 u8 zero_based_page_size_log; 453 __le32 l_key; 454 u8 length[5]; 455 u8 reserved8_1; 456 u8 reserved8_2; 457 u8 numlevels_pbl_page_size_log; 458 __le64 pblptr; 459 __le64 va; 460 }; 461 462 /* Bind SQ WQE (40 bytes) */ 463 struct sq_bind { 464 u8 wqe_type; 465 #define SQ_BIND_WQE_TYPE_BIND 0xeUL 466 u8 flags; 467 #define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL 468 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 469 #define SQ_BIND_FLAGS_UC_FENCE 0x4UL 470 #define SQ_BIND_FLAGS_SE 0x8UL 471 #define SQ_BIND_FLAGS_INLINE 0x10UL 472 u8 access_cntl; 473 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL 474 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL 475 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL 476 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 477 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL 478 u8 reserved8_1; 479 u8 mw_type_zero_based; 480 #define SQ_BIND_ZERO_BASED 0x1UL 481 #define SQ_BIND_MW_TYPE 0x2UL 482 #define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1) 483 #define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1) 484 #define SQ_BIND_RESERVED6_MASK 0xfcUL 485 #define SQ_BIND_RESERVED6_SFT 2 486 u8 reserved8_2; 487 __le16 reserved16; 488 __le32 parent_l_key; 489 __le32 l_key; 490 __le64 va; 491 u8 length[5]; 492 u8 data_reserved24[99]; 493 #define SQ_BIND_RESERVED24_MASK 0xffffff00UL 494 #define SQ_BIND_RESERVED24_SFT 8 495 #define SQ_BIND_DATA_MASK 0xffffffffUL 496 #define SQ_BIND_DATA_SFT 0 497 }; 498 499 /* sq_bind_hdr (size:256b/32B) */ 500 struct sq_bind_hdr { 501 u8 wqe_type; 502 u8 flags; 503 u8 access_cntl; 504 u8 reserved8_1; 505 u8 mw_type_zero_based; 506 u8 reserved8_2; 507 __le16 reserved16; 508 __le32 parent_l_key; 509 __le32 l_key; 510 __le64 va; 511 u8 length[5]; 512 u8 reserved24[3]; 513 }; 514 515 /* RQ/SRQ WQE Structures */ 516 /* RQ/SRQ WQE (40 bytes) */ 517 struct rq_wqe { 518 u8 wqe_type; 519 #define RQ_WQE_WQE_TYPE_RCV 0x80UL 520 u8 flags; 521 u8 wqe_size; 522 u8 reserved8; 523 __le32 reserved32; 524 __le32 wr_id[2]; 525 #define RQ_WQE_WR_ID_MASK 0xfffffUL 526 #define RQ_WQE_WR_ID_SFT 0 527 #define RQ_WQE_RESERVED44_MASK 0xfff00000UL 528 #define RQ_WQE_RESERVED44_SFT 20 529 __le32 reserved128[4]; 530 __le32 data[24]; 531 }; 532 533 /* rq_wqe_hdr (size:256b/32B) */ 534 struct rq_wqe_hdr { 535 u8 wqe_type; 536 u8 flags; 537 u8 wqe_size; 538 u8 reserved8; 539 __le32 reserved32; 540 __le32 wr_id[2]; 541 u8 reserved128[16]; 542 }; 543 544 /* CQ CQE Structures */ 545 /* Base CQE (32 bytes) */ 546 struct cq_base { 547 __le64 reserved64_1; 548 __le64 reserved64_2; 549 __le64 reserved64_3; 550 u8 cqe_type_toggle; 551 #define CQ_BASE_TOGGLE 0x1UL 552 #define CQ_BASE_CQE_TYPE_MASK 0x1eUL 553 #define CQ_BASE_CQE_TYPE_SFT 1 554 #define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1) 555 #define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1) 556 #define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1) 557 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 558 #define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1) 559 #define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1) 560 #define CQ_BASE_RESERVED3_MASK 0xe0UL 561 #define CQ_BASE_RESERVED3_SFT 5 562 u8 status; 563 __le16 reserved16; 564 __le32 reserved32; 565 }; 566 567 /* Requester CQ CQE (32 bytes) */ 568 struct cq_req { 569 __le64 qp_handle; 570 __le16 sq_cons_idx; 571 __le16 reserved16_1; 572 __le32 reserved32_2; 573 __le64 reserved64; 574 u8 cqe_type_toggle; 575 #define CQ_REQ_TOGGLE 0x1UL 576 #define CQ_REQ_CQE_TYPE_MASK 0x1eUL 577 #define CQ_REQ_CQE_TYPE_SFT 1 578 #define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1) 579 #define CQ_REQ_RESERVED3_MASK 0xe0UL 580 #define CQ_REQ_RESERVED3_SFT 5 581 u8 status; 582 #define CQ_REQ_STATUS_OK 0x0UL 583 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL 584 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL 585 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL 586 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL 587 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 588 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 589 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL 590 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL 591 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL 592 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL 593 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL 594 __le16 reserved16_2; 595 __le32 reserved32_1; 596 }; 597 598 /* Responder RC CQE (32 bytes) */ 599 struct cq_res_rc { 600 __le32 length; 601 __le32 imm_data_or_inv_r_key; 602 __le64 qp_handle; 603 __le64 mr_handle; 604 u8 cqe_type_toggle; 605 #define CQ_RES_RC_TOGGLE 0x1UL 606 #define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL 607 #define CQ_RES_RC_CQE_TYPE_SFT 1 608 #define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1) 609 #define CQ_RES_RC_RESERVED3_MASK 0xe0UL 610 #define CQ_RES_RC_RESERVED3_SFT 5 611 u8 status; 612 #define CQ_RES_RC_STATUS_OK 0x0UL 613 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL 614 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL 615 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL 616 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 617 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 618 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 619 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 620 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL 621 __le16 flags; 622 #define CQ_RES_RC_FLAGS_SRQ 0x1UL 623 #define CQ_RES_RC_FLAGS_SRQ_RQ (0x0UL << 0) 624 #define CQ_RES_RC_FLAGS_SRQ_SRQ (0x1UL << 0) 625 #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ 626 #define CQ_RES_RC_FLAGS_IMM 0x2UL 627 #define CQ_RES_RC_FLAGS_INV 0x4UL 628 #define CQ_RES_RC_FLAGS_RDMA 0x8UL 629 #define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3) 630 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3) 631 #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE 632 __le32 srq_or_rq_wr_id; 633 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 634 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0 635 #define CQ_RES_RC_RESERVED12_MASK 0xfff00000UL 636 #define CQ_RES_RC_RESERVED12_SFT 20 637 }; 638 639 /* Responder UD CQE (32 bytes) */ 640 struct cq_res_ud { 641 __le16 length; 642 #define CQ_RES_UD_LENGTH_MASK 0x3fffUL 643 #define CQ_RES_UD_LENGTH_SFT 0 644 __le16 cfa_metadata; 645 #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL 646 #define CQ_RES_UD_CFA_METADATA_VID_SFT 0 647 #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL 648 #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL 649 #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13 650 __le32 imm_data; 651 __le64 qp_handle; 652 __le16 src_mac[3]; 653 __le16 src_qp_low; 654 u8 cqe_type_toggle; 655 #define CQ_RES_UD_TOGGLE 0x1UL 656 #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL 657 #define CQ_RES_UD_CQE_TYPE_SFT 1 658 #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1) 659 u8 status; 660 #define CQ_RES_UD_STATUS_OK 0x0UL 661 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL 662 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 663 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL 664 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 665 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 666 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 667 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL 668 __le16 flags; 669 #define CQ_RES_UD_FLAGS_SRQ 0x1UL 670 #define CQ_RES_UD_FLAGS_SRQ_RQ (0x0UL << 0) 671 #define CQ_RES_UD_FLAGS_SRQ_SRQ (0x1UL << 0) 672 #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ 673 #define CQ_RES_UD_FLAGS_IMM 0x2UL 674 #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL 675 #define CQ_RES_UD_FLAGS_UNUSED_SFT 2 676 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL 677 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4 678 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 679 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 680 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 681 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST \ 682 CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 683 #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL 684 #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 685 #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6) 686 #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 687 #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 688 #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 689 #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 690 #define CQ_RES_UD_FLAGS_META_FORMAT_LAST \ 691 CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET 692 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 693 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10 694 695 __le32 src_qp_high_srq_or_rq_wr_id; 696 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 697 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0 698 #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL 699 #define CQ_RES_UD_SRC_QP_HIGH_SFT 24 700 }; 701 702 /* Responder RawEth and QP1 CQE (32 bytes) */ 703 struct cq_res_raweth_qp1 { 704 __le16 length; 705 #define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL 706 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0 707 #define CQ_RES_RAWETH_QP1_RESERVED2_MASK 0xc000UL 708 #define CQ_RES_RAWETH_QP1_RESERVED2_SFT 14 709 __le16 raweth_qp1_flags; 710 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL 711 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_MASK 0x3eUL 712 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_SFT 1 713 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 714 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6 715 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 716 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 717 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 718 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 719 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 720 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 721 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 722 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ 723 (0x8UL << 6) 724 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP \ 725 (0x9UL << 6) 726 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST \ 727 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 728 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL 729 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 730 #define CQ_RES_RAWETH_QP1_RESERVED6_MASK 0xfc00UL 731 #define CQ_RES_RAWETH_QP1_RESERVED6_SFT 10 732 __le16 raweth_qp1_errors; 733 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_MASK 0xfUL 734 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_SFT 0 735 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 736 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 737 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 738 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 739 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 740 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 741 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 742 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR \ 743 (0x0UL << 9) 744 #define \ 745 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \ 746 (0x1UL << 9) 747 #define \ 748 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \ 749 (0x2UL << 9) 750 #define \ 751 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \ 752 (0x3UL << 9) 753 #define \ 754 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \ 755 (0x4UL << 9) 756 #define \ 757 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \ 758 (0x5UL << 9) 759 #define \ 760 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \ 761 (0x6UL << 9) 762 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 763 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 764 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 765 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 766 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR \ 767 (0x0UL << 12) 768 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION \ 769 (0x1UL << 12) 770 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \ 771 (0x2UL << 12) 772 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL \ 773 (0x3UL << 12) 774 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \ 775 (0x4UL << 12) 776 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \ 777 (0x5UL << 12) 778 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \ 779 (0x6UL << 12) 780 #define \ 781 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL\ 782 (0x7UL << 12) 783 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ 784 (0x8UL << 12) 785 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 786 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 787 __le16 raweth_qp1_cfa_code; 788 __le64 qp_handle; 789 __le32 raweth_qp1_flags2; 790 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL 791 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL 792 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL 793 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL 794 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 795 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 796 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE \ 797 (0x0UL << 4) 798 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN \ 799 (0x1UL << 4) 800 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST\ 801 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN 802 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 803 __le32 raweth_qp1_metadata; 804 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL 805 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0 806 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL 807 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL 808 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13 809 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL 810 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16 811 u8 cqe_type_toggle; 812 #define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL 813 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL 814 #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 815 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 816 #define CQ_RES_RAWETH_QP1_RESERVED3_MASK 0xe0UL 817 #define CQ_RES_RAWETH_QP1_RESERVED3_SFT 5 818 u8 status; 819 #define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL 820 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL 821 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 822 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL 823 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 824 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 825 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 826 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL 827 __le16 flags; 828 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL 829 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL 830 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL 831 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST \ 832 CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 833 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 834 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 835 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 836 #define CQ_RES_RAWETH_QP1_RESERVED4_MASK 0xf00000UL 837 #define CQ_RES_RAWETH_QP1_RESERVED4_SFT 20 838 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 839 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 840 }; 841 842 /* Terminal CQE (32 bytes) */ 843 struct cq_terminal { 844 __le64 qp_handle; 845 __le16 sq_cons_idx; 846 __le16 rq_cons_idx; 847 __le32 reserved32_1; 848 __le64 reserved64_3; 849 u8 cqe_type_toggle; 850 #define CQ_TERMINAL_TOGGLE 0x1UL 851 #define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL 852 #define CQ_TERMINAL_CQE_TYPE_SFT 1 853 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1) 854 #define CQ_TERMINAL_RESERVED3_MASK 0xe0UL 855 #define CQ_TERMINAL_RESERVED3_SFT 5 856 u8 status; 857 #define CQ_TERMINAL_STATUS_OK 0x0UL 858 __le16 reserved16; 859 __le32 reserved32_2; 860 }; 861 862 /* Cutoff CQE (32 bytes) */ 863 struct cq_cutoff { 864 __le64 reserved64_1; 865 __le64 reserved64_2; 866 __le64 reserved64_3; 867 u8 cqe_type_toggle; 868 #define CQ_CUTOFF_TOGGLE 0x1UL 869 #define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL 870 #define CQ_CUTOFF_CQE_TYPE_SFT 1 871 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1) 872 #define CQ_CUTOFF_RESERVED3_MASK 0xe0UL 873 #define CQ_CUTOFF_RESERVED3_SFT 5 874 u8 status; 875 #define CQ_CUTOFF_STATUS_OK 0x0UL 876 __le16 reserved16; 877 __le32 reserved32; 878 }; 879 880 /* Notification Queue (NQ) Structures */ 881 /* Base NQ Record (16 bytes) */ 882 struct nq_base { 883 __le16 info10_type; 884 #define NQ_BASE_TYPE_MASK 0x3fUL 885 #define NQ_BASE_TYPE_SFT 0 886 #define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL 887 #define NQ_BASE_TYPE_SRQ_EVENT 0x32UL 888 #define NQ_BASE_TYPE_DBQ_EVENT 0x34UL 889 #define NQ_BASE_TYPE_QP_EVENT 0x38UL 890 #define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL 891 #define NQ_BASE_INFO10_MASK 0xffc0UL 892 #define NQ_BASE_INFO10_SFT 6 893 __le16 info16; 894 __le32 info32; 895 __le32 info63_v[2]; 896 #define NQ_BASE_V 0x1UL 897 #define NQ_BASE_INFO63_MASK 0xfffffffeUL 898 #define NQ_BASE_INFO63_SFT 1 899 }; 900 901 /* Completion Queue Notification (16 bytes) */ 902 struct nq_cn { 903 __le16 type; 904 #define NQ_CN_TYPE_MASK 0x3fUL 905 #define NQ_CN_TYPE_SFT 0 906 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 907 #define NQ_CN_RESERVED9_MASK 0xffc0UL 908 #define NQ_CN_RESERVED9_SFT 6 909 __le16 reserved16; 910 __le32 cq_handle_low; 911 __le32 v; 912 #define NQ_CN_V 0x1UL 913 #define NQ_CN_RESERVED31_MASK 0xfffffffeUL 914 #define NQ_CN_RESERVED31_SFT 1 915 __le32 cq_handle_high; 916 }; 917 918 /* SRQ Event Notification (16 bytes) */ 919 struct nq_srq_event { 920 u8 type; 921 #define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL 922 #define NQ_SRQ_EVENT_TYPE_SFT 0 923 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL 924 #define NQ_SRQ_EVENT_RESERVED1_MASK 0xc0UL 925 #define NQ_SRQ_EVENT_RESERVED1_SFT 6 926 u8 event; 927 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL 928 __le16 reserved16; 929 __le32 srq_handle_low; 930 __le32 v; 931 #define NQ_SRQ_EVENT_V 0x1UL 932 #define NQ_SRQ_EVENT_RESERVED31_MASK 0xfffffffeUL 933 #define NQ_SRQ_EVENT_RESERVED31_SFT 1 934 __le32 srq_handle_high; 935 }; 936 937 /* DBQ Async Event Notification (16 bytes) */ 938 struct nq_dbq_event { 939 u8 type; 940 #define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL 941 #define NQ_DBQ_EVENT_TYPE_SFT 0 942 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL 943 #define NQ_DBQ_EVENT_RESERVED1_MASK 0xc0UL 944 #define NQ_DBQ_EVENT_RESERVED1_SFT 6 945 u8 event; 946 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL 947 __le16 db_pfid; 948 #define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL 949 #define NQ_DBQ_EVENT_DB_PFID_SFT 0 950 #define NQ_DBQ_EVENT_RESERVED12_MASK 0xfff0UL 951 #define NQ_DBQ_EVENT_RESERVED12_SFT 4 952 __le32 db_dpi; 953 #define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL 954 #define NQ_DBQ_EVENT_DB_DPI_SFT 0 955 #define NQ_DBQ_EVENT_RESERVED12_2_MASK 0xfff00000UL 956 #define NQ_DBQ_EVENT_RESERVED12_2_SFT 20 957 __le32 v; 958 #define NQ_DBQ_EVENT_V 0x1UL 959 #define NQ_DBQ_EVENT_RESERVED32_MASK 0xfffffffeUL 960 #define NQ_DBQ_EVENT_RESERVED32_SFT 1 961 __le32 db_type_db_xid; 962 #define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL 963 #define NQ_DBQ_EVENT_DB_XID_SFT 0 964 #define NQ_DBQ_EVENT_RESERVED8_MASK 0xff00000UL 965 #define NQ_DBQ_EVENT_RESERVED8_SFT 20 966 #define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL 967 #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 968 }; 969 970 /* Read Request/Response Queue Structures */ 971 /* Input Read Request Queue (IRRQ) Message (32 bytes) */ 972 struct xrrq_irrq { 973 __le16 credits_type; 974 #define XRRQ_IRRQ_TYPE 0x1UL 975 #define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL 976 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL 977 #define XRRQ_IRRQ_RESERVED10_MASK 0x7feUL 978 #define XRRQ_IRRQ_RESERVED10_SFT 1 979 #define XRRQ_IRRQ_CREDITS_MASK 0xf800UL 980 #define XRRQ_IRRQ_CREDITS_SFT 11 981 __le16 reserved16; 982 __le32 reserved32; 983 __le32 psn; 984 #define XRRQ_IRRQ_PSN_MASK 0xffffffUL 985 #define XRRQ_IRRQ_PSN_SFT 0 986 #define XRRQ_IRRQ_RESERVED8_1_MASK 0xff000000UL 987 #define XRRQ_IRRQ_RESERVED8_1_SFT 24 988 __le32 msn; 989 #define XRRQ_IRRQ_MSN_MASK 0xffffffUL 990 #define XRRQ_IRRQ_MSN_SFT 0 991 #define XRRQ_IRRQ_RESERVED8_2_MASK 0xff000000UL 992 #define XRRQ_IRRQ_RESERVED8_2_SFT 24 993 __le64 va_or_atomic_result; 994 __le32 rdma_r_key; 995 __le32 length; 996 }; 997 998 /* Output Read Request Queue (ORRQ) Message (32 bytes) */ 999 struct xrrq_orrq { 1000 __le16 num_sges_type; 1001 #define XRRQ_ORRQ_TYPE 0x1UL 1002 #define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL 1003 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL 1004 #define XRRQ_ORRQ_RESERVED10_MASK 0x7feUL 1005 #define XRRQ_ORRQ_RESERVED10_SFT 1 1006 #define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL 1007 #define XRRQ_ORRQ_NUM_SGES_SFT 11 1008 __le16 reserved16; 1009 __le32 length; 1010 __le32 psn; 1011 #define XRRQ_ORRQ_PSN_MASK 0xffffffUL 1012 #define XRRQ_ORRQ_PSN_SFT 0 1013 #define XRRQ_ORRQ_RESERVED8_1_MASK 0xff000000UL 1014 #define XRRQ_ORRQ_RESERVED8_1_SFT 24 1015 __le32 end_psn; 1016 #define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL 1017 #define XRRQ_ORRQ_END_PSN_SFT 0 1018 #define XRRQ_ORRQ_RESERVED8_2_MASK 0xff000000UL 1019 #define XRRQ_ORRQ_RESERVED8_2_SFT 24 1020 __le64 first_sge_phy_or_sing_sge_va; 1021 __le32 single_sge_l_key; 1022 __le32 single_sge_size; 1023 }; 1024 1025 /* Page Buffer List Memory Structures (PBL) */ 1026 /* Page Table Entry (PTE) (8 bytes) */ 1027 struct ptu_pte { 1028 __le32 page_next_to_last_last_valid[2]; 1029 #define PTU_PTE_VALID 0x1UL 1030 #define PTU_PTE_LAST 0x2UL 1031 #define PTU_PTE_NEXT_TO_LAST 0x4UL 1032 #define PTU_PTE_PAGE_MASK 0xfffff000UL 1033 #define PTU_PTE_PAGE_SFT 12 1034 }; 1035 1036 /* Page Directory Entry (PDE) (8 bytes) */ 1037 struct ptu_pde { 1038 __le32 page_valid[2]; 1039 #define PTU_PDE_VALID 0x1UL 1040 #define PTU_PDE_PAGE_MASK 0xfffff000UL 1041 #define PTU_PDE_PAGE_SFT 12 1042 }; 1043 1044 /* RoCE Fastpath Host Structures */ 1045 /* Command Queue (CMDQ) Interface */ 1046 /* Init CMDQ (16 bytes) */ 1047 struct cmdq_init { 1048 __le64 cmdq_pbl; 1049 __le16 cmdq_size_cmdq_lvl; 1050 #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL 1051 #define CMDQ_INIT_CMDQ_LVL_SFT 0 1052 #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL 1053 #define CMDQ_INIT_CMDQ_SIZE_SFT 2 1054 __le16 creq_ring_id; 1055 __le32 prod_idx; 1056 }; 1057 1058 /* Update CMDQ producer index (16 bytes) */ 1059 struct cmdq_update { 1060 __le64 reserved64; 1061 __le32 reserved32; 1062 __le32 prod_idx; 1063 }; 1064 1065 /* CMDQ common header structure (16 bytes) */ 1066 struct cmdq_base { 1067 u8 opcode; 1068 #define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL 1069 #define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL 1070 #define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL 1071 #define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL 1072 #define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL 1073 #define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL 1074 #define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL 1075 #define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL 1076 #define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL 1077 #define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL 1078 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL 1079 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL 1080 #define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL 1081 #define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL 1082 #define CMDQ_BASE_OPCODE_ADD_GID 0x11UL 1083 #define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL 1084 #define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL 1085 #define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL 1086 #define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL 1087 #define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL 1088 #define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL 1089 #define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL 1090 #define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL 1091 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL 1092 #define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL 1093 #define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL 1094 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL 1095 #define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL 1096 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL 1097 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL 1098 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL 1099 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY 0x89UL 1100 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL 1101 #define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL 1102 #define CMDQ_BASE_OPCODE_MODIFY_CC 0x8cUL 1103 #define CMDQ_BASE_OPCODE_QUERY_CC 0x8dUL 1104 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL 1105 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 1106 u8 cmd_size; 1107 __le16 flags; 1108 __le16 cookie; 1109 u8 resp_size; 1110 u8 reserved8; 1111 __le64 resp_addr; 1112 }; 1113 1114 /* Create QP command (96 bytes) */ 1115 struct cmdq_create_qp { 1116 u8 opcode; 1117 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL 1118 u8 cmd_size; 1119 __le16 flags; 1120 __le16 cookie; 1121 u8 resp_size; 1122 u8 reserved8; 1123 __le64 resp_addr; 1124 __le64 qp_handle; 1125 __le32 qp_flags; 1126 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL 1127 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL 1128 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 1129 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL 1130 #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL 1131 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL 1132 #define CMDQ_CREATE_QP_QP_FLAGS_LAST \ 1133 CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 1134 1135 u8 type; 1136 #define CMDQ_CREATE_QP_TYPE_RC 0x2UL 1137 #define CMDQ_CREATE_QP_TYPE_UD 0x4UL 1138 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL 1139 #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL 1140 u8 sq_pg_size_sq_lvl; 1141 #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL 1142 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 1143 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL 1144 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL 1145 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL 1146 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL 1147 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 1148 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4) 1149 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4) 1150 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4) 1151 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4) 1152 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4) 1153 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4) 1154 u8 rq_pg_size_rq_lvl; 1155 #define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL 1156 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 1157 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL 1158 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL 1159 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL 1160 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL 1161 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 1162 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4) 1163 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4) 1164 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4) 1165 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4) 1166 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4) 1167 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4) 1168 u8 unused_0; 1169 __le32 dpi; 1170 __le32 sq_size; 1171 __le32 rq_size; 1172 __le16 sq_fwo_sq_sge; 1173 #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL 1174 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 1175 #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL 1176 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 1177 __le16 rq_fwo_rq_sge; 1178 #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL 1179 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 1180 #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL 1181 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 1182 __le32 scq_cid; 1183 __le32 rcq_cid; 1184 __le32 srq_cid; 1185 __le32 pd_id; 1186 __le64 sq_pbl; 1187 __le64 rq_pbl; 1188 __le64 irrq_addr; 1189 __le64 orrq_addr; 1190 }; 1191 1192 /* Destroy QP command (24 bytes) */ 1193 struct cmdq_destroy_qp { 1194 u8 opcode; 1195 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL 1196 u8 cmd_size; 1197 __le16 flags; 1198 __le16 cookie; 1199 u8 resp_size; 1200 u8 reserved8; 1201 __le64 resp_addr; 1202 __le32 qp_cid; 1203 __le32 unused_0; 1204 }; 1205 1206 /* Modify QP command (112 bytes) */ 1207 struct cmdq_modify_qp { 1208 u8 opcode; 1209 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL 1210 u8 cmd_size; 1211 __le16 flags; 1212 __le16 cookie; 1213 u8 resp_size; 1214 u8 reserved8; 1215 __le64 resp_addr; 1216 __le32 modify_mask; 1217 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL 1218 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL 1219 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL 1220 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL 1221 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL 1222 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL 1223 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL 1224 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL 1225 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL 1226 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL 1227 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL 1228 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL 1229 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL 1230 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL 1231 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL 1232 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL 1233 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL 1234 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL 1235 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL 1236 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL 1237 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL 1238 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL 1239 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL 1240 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL 1241 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL 1242 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL 1243 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL 1244 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL 1245 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL 1246 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL 1247 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL 1248 __le32 qp_cid; 1249 u8 network_type_en_sqd_async_notify_new_state; 1250 #define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL 1251 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0 1252 #define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL 1253 #define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL 1254 #define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL 1255 #define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL 1256 #define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL 1257 #define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL 1258 #define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL 1259 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL 1260 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL 1261 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6 1262 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6) 1263 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6) 1264 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6) 1265 u8 access; 1266 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL 1267 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL 1268 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL 1269 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL 1270 __le16 pkey; 1271 __le32 qkey; 1272 __le32 dgid[4]; 1273 __le32 flow_label; 1274 __le16 sgid_index; 1275 u8 hop_limit; 1276 u8 traffic_class; 1277 __le16 dest_mac[3]; 1278 u8 tos_dscp_tos_ecn; 1279 #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL 1280 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0 1281 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL 1282 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2 1283 u8 path_mtu; 1284 #define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL 1285 #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4 1286 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4) 1287 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4) 1288 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4) 1289 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4) 1290 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4) 1291 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4) 1292 u8 timeout; 1293 u8 retry_cnt; 1294 u8 rnr_retry; 1295 u8 min_rnr_timer; 1296 __le32 rq_psn; 1297 __le32 sq_psn; 1298 u8 max_rd_atomic; 1299 u8 max_dest_rd_atomic; 1300 __le16 enable_cc; 1301 #define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL 1302 __le32 sq_size; 1303 __le32 rq_size; 1304 __le16 sq_sge; 1305 __le16 rq_sge; 1306 __le32 max_inline_data; 1307 __le32 dest_qp_id; 1308 __le32 unused_3; 1309 __le16 src_mac[3]; 1310 __le16 vlan_pcp_vlan_dei_vlan_id; 1311 #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL 1312 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0 1313 #define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL 1314 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL 1315 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13 1316 }; 1317 1318 /* Query QP command (24 bytes) */ 1319 struct cmdq_query_qp { 1320 u8 opcode; 1321 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL 1322 u8 cmd_size; 1323 __le16 flags; 1324 __le16 cookie; 1325 u8 resp_size; 1326 u8 reserved8; 1327 __le64 resp_addr; 1328 __le32 qp_cid; 1329 __le32 unused_0; 1330 }; 1331 1332 /* Create SRQ command (48 bytes) */ 1333 struct cmdq_create_srq { 1334 u8 opcode; 1335 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL 1336 u8 cmd_size; 1337 __le16 flags; 1338 __le16 cookie; 1339 u8 resp_size; 1340 u8 reserved8; 1341 __le64 resp_addr; 1342 __le64 srq_handle; 1343 __le16 pg_size_lvl; 1344 #define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL 1345 #define CMDQ_CREATE_SRQ_LVL_SFT 0 1346 #define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL 1347 #define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL 1348 #define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL 1349 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL 1350 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2 1351 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2) 1352 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2) 1353 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2) 1354 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2) 1355 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2) 1356 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2) 1357 __le16 eventq_id; 1358 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL 1359 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0 1360 __le16 srq_size; 1361 __le16 srq_fwo; 1362 __le32 dpi; 1363 __le32 pd_id; 1364 __le64 pbl; 1365 }; 1366 1367 /* Destroy SRQ command (24 bytes) */ 1368 struct cmdq_destroy_srq { 1369 u8 opcode; 1370 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL 1371 u8 cmd_size; 1372 __le16 flags; 1373 __le16 cookie; 1374 u8 resp_size; 1375 u8 reserved8; 1376 __le64 resp_addr; 1377 __le32 srq_cid; 1378 __le32 unused_0; 1379 }; 1380 1381 /* Query SRQ command (24 bytes) */ 1382 struct cmdq_query_srq { 1383 u8 opcode; 1384 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL 1385 u8 cmd_size; 1386 __le16 flags; 1387 __le16 cookie; 1388 u8 resp_size; 1389 u8 reserved8; 1390 __le64 resp_addr; 1391 __le32 srq_cid; 1392 __le32 unused_0; 1393 }; 1394 1395 /* Create CQ command (48 bytes) */ 1396 struct cmdq_create_cq { 1397 u8 opcode; 1398 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL 1399 u8 cmd_size; 1400 __le16 flags; 1401 __le16 cookie; 1402 u8 resp_size; 1403 u8 reserved8; 1404 __le64 resp_addr; 1405 __le64 cq_handle; 1406 __le32 pg_size_lvl; 1407 #define CMDQ_CREATE_CQ_LVL_MASK 0x3UL 1408 #define CMDQ_CREATE_CQ_LVL_SFT 0 1409 #define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL 1410 #define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL 1411 #define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL 1412 #define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL 1413 #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2 1414 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1415 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1416 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1417 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1418 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1419 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1420 __le32 cq_fco_cnq_id; 1421 #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL 1422 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0 1423 #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL 1424 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12 1425 __le32 dpi; 1426 __le32 cq_size; 1427 __le64 pbl; 1428 }; 1429 1430 /* Destroy CQ command (24 bytes) */ 1431 struct cmdq_destroy_cq { 1432 u8 opcode; 1433 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL 1434 u8 cmd_size; 1435 __le16 flags; 1436 __le16 cookie; 1437 u8 resp_size; 1438 u8 reserved8; 1439 __le64 resp_addr; 1440 __le32 cq_cid; 1441 __le32 unused_0; 1442 }; 1443 1444 /* Resize CQ command (40 bytes) */ 1445 struct cmdq_resize_cq { 1446 u8 opcode; 1447 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL 1448 u8 cmd_size; 1449 __le16 flags; 1450 __le16 cookie; 1451 u8 resp_size; 1452 u8 reserved8; 1453 __le64 resp_addr; 1454 __le32 cq_cid; 1455 __le32 new_cq_size_pg_size_lvl; 1456 #define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL 1457 #define CMDQ_RESIZE_CQ_LVL_SFT 0 1458 #define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL 1459 #define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL 1460 #define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL 1461 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL 1462 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2 1463 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1464 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1465 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1466 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1467 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1468 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1469 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffe0UL 1470 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5 1471 __le64 new_pbl; 1472 __le32 new_cq_fco; 1473 __le32 unused_2; 1474 }; 1475 1476 /* Allocate MRW command (32 bytes) */ 1477 struct cmdq_allocate_mrw { 1478 u8 opcode; 1479 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL 1480 u8 cmd_size; 1481 __le16 flags; 1482 __le16 cookie; 1483 u8 resp_size; 1484 u8 reserved8; 1485 __le64 resp_addr; 1486 __le64 mrw_handle; 1487 u8 mrw_flags; 1488 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL 1489 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 1490 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL 1491 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL 1492 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL 1493 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL 1494 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL 1495 u8 access; 1496 #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_MASK 0x1fUL 1497 #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_SFT 0 1498 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL 1499 __le16 unused_1; 1500 __le32 pd_id; 1501 }; 1502 1503 /* De-allocate key command (24 bytes) */ 1504 struct cmdq_deallocate_key { 1505 u8 opcode; 1506 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL 1507 u8 cmd_size; 1508 __le16 flags; 1509 __le16 cookie; 1510 u8 resp_size; 1511 u8 reserved8; 1512 __le64 resp_addr; 1513 u8 mrw_flags; 1514 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL 1515 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0 1516 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL 1517 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL 1518 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL 1519 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL 1520 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL 1521 u8 unused_1[3]; 1522 __le32 key; 1523 }; 1524 1525 /* Register MR command (48 bytes) */ 1526 struct cmdq_register_mr { 1527 u8 opcode; 1528 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL 1529 u8 cmd_size; 1530 __le16 flags; 1531 __le16 cookie; 1532 u8 resp_size; 1533 u8 reserved8; 1534 __le64 resp_addr; 1535 u8 log2_pg_size_lvl; 1536 #define CMDQ_REGISTER_MR_LVL_MASK 0x3UL 1537 #define CMDQ_REGISTER_MR_LVL_SFT 0 1538 #define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL 1539 #define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL 1540 #define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL 1541 #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 1542 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL 1543 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 1544 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2) 1545 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2) 1546 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2) 1547 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2) 1548 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2) 1549 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2) 1550 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2) 1551 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2) 1552 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST \ 1553 CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G 1554 #define CMDQ_REGISTER_MR_UNUSED1 0x80UL 1555 u8 access; 1556 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL 1557 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL 1558 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL 1559 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL 1560 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL 1561 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL 1562 __le16 log2_pbl_pg_size; 1563 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL 1564 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 1565 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL 1566 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL 1567 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL 1568 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL 1569 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL 1570 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL 1571 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL 1572 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL 1573 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST \ 1574 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 1575 #define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL 1576 #define CMDQ_REGISTER_MR_UNUSED11_SFT 5 1577 __le32 key; 1578 __le64 pbl; 1579 __le64 va; 1580 __le64 mr_size; 1581 }; 1582 1583 /* Deregister MR command (24 bytes) */ 1584 struct cmdq_deregister_mr { 1585 u8 opcode; 1586 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL 1587 u8 cmd_size; 1588 __le16 flags; 1589 __le16 cookie; 1590 u8 resp_size; 1591 u8 reserved8; 1592 __le64 resp_addr; 1593 __le32 lkey; 1594 __le32 unused_0; 1595 }; 1596 1597 /* Add GID command (48 bytes) */ 1598 struct cmdq_add_gid { 1599 u8 opcode; 1600 #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL 1601 u8 cmd_size; 1602 __le16 flags; 1603 __le16 cookie; 1604 u8 resp_size; 1605 u8 reserved8; 1606 __le64 resp_addr; 1607 __be32 gid[4]; 1608 __be16 src_mac[3]; 1609 __le16 vlan; 1610 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL 1611 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0 1612 #define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL 1613 #define CMDQ_ADD_GID_VLAN_TPID_SFT 12 1614 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1615 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1616 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1617 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1618 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1619 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1620 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1621 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1622 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 1623 #define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL 1624 __le16 ipid; 1625 __le16 stats_ctx; 1626 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1627 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1628 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1629 __le32 unused_0; 1630 }; 1631 1632 /* Delete GID command (24 bytes) */ 1633 struct cmdq_delete_gid { 1634 u8 opcode; 1635 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL 1636 u8 cmd_size; 1637 __le16 flags; 1638 __le16 cookie; 1639 u8 resp_size; 1640 u8 reserved8; 1641 __le64 resp_addr; 1642 __le16 gid_index; 1643 __le16 unused_0; 1644 __le32 unused_1; 1645 }; 1646 1647 /* Modify GID command (48 bytes) */ 1648 struct cmdq_modify_gid { 1649 u8 opcode; 1650 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL 1651 u8 cmd_size; 1652 __le16 flags; 1653 __le16 cookie; 1654 u8 resp_size; 1655 u8 reserved8; 1656 __le64 resp_addr; 1657 __be32 gid[4]; 1658 __be16 src_mac[3]; 1659 __le16 vlan; 1660 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL 1661 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0 1662 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL 1663 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12 1664 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1665 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1666 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1667 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1668 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1669 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1670 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1671 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1672 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST \ 1673 CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 1674 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL 1675 __le16 ipid; 1676 __le16 gid_index; 1677 __le16 stats_ctx; 1678 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1679 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1680 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1681 __le16 unused_0; 1682 }; 1683 1684 /* Query GID command (24 bytes) */ 1685 struct cmdq_query_gid { 1686 u8 opcode; 1687 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL 1688 u8 cmd_size; 1689 __le16 flags; 1690 __le16 cookie; 1691 u8 resp_size; 1692 u8 reserved8; 1693 __le64 resp_addr; 1694 __le16 gid_index; 1695 __le16 unused_0; 1696 __le32 unused_1; 1697 }; 1698 1699 /* Create QP1 command (80 bytes) */ 1700 struct cmdq_create_qp1 { 1701 u8 opcode; 1702 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL 1703 u8 cmd_size; 1704 __le16 flags; 1705 __le16 cookie; 1706 u8 resp_size; 1707 u8 reserved8; 1708 __le64 resp_addr; 1709 __le64 qp_handle; 1710 __le32 qp_flags; 1711 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL 1712 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL 1713 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 1714 u8 type; 1715 #define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL 1716 u8 sq_pg_size_sq_lvl; 1717 #define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL 1718 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0 1719 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL 1720 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL 1721 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL 1722 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL 1723 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4 1724 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4) 1725 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4) 1726 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4) 1727 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4) 1728 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4) 1729 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4) 1730 u8 rq_pg_size_rq_lvl; 1731 #define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL 1732 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0 1733 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL 1734 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL 1735 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL 1736 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL 1737 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4 1738 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4) 1739 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4) 1740 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4) 1741 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4) 1742 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4) 1743 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4) 1744 u8 unused_0; 1745 __le32 dpi; 1746 __le32 sq_size; 1747 __le32 rq_size; 1748 __le16 sq_fwo_sq_sge; 1749 #define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL 1750 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0 1751 #define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL 1752 #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4 1753 __le16 rq_fwo_rq_sge; 1754 #define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL 1755 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0 1756 #define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL 1757 #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4 1758 __le32 scq_cid; 1759 __le32 rcq_cid; 1760 __le32 srq_cid; 1761 __le32 pd_id; 1762 __le64 sq_pbl; 1763 __le64 rq_pbl; 1764 }; 1765 1766 /* Destroy QP1 command (24 bytes) */ 1767 struct cmdq_destroy_qp1 { 1768 u8 opcode; 1769 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL 1770 u8 cmd_size; 1771 __le16 flags; 1772 __le16 cookie; 1773 u8 resp_size; 1774 u8 reserved8; 1775 __le64 resp_addr; 1776 __le32 qp1_cid; 1777 __le32 unused_0; 1778 }; 1779 1780 /* Create AH command (64 bytes) */ 1781 struct cmdq_create_ah { 1782 u8 opcode; 1783 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL 1784 u8 cmd_size; 1785 __le16 flags; 1786 __le16 cookie; 1787 u8 resp_size; 1788 u8 reserved8; 1789 __le64 resp_addr; 1790 __le64 ah_handle; 1791 __le32 dgid[4]; 1792 u8 type; 1793 #define CMDQ_CREATE_AH_TYPE_V1 0x0UL 1794 #define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL 1795 #define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL 1796 u8 hop_limit; 1797 __le16 sgid_index; 1798 __le32 dest_vlan_id_flow_label; 1799 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL 1800 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0 1801 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL 1802 #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20 1803 __le32 pd_id; 1804 __le32 unused_0; 1805 __le16 dest_mac[3]; 1806 u8 traffic_class; 1807 u8 unused_1; 1808 }; 1809 1810 /* Destroy AH command (24 bytes) */ 1811 struct cmdq_destroy_ah { 1812 u8 opcode; 1813 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL 1814 u8 cmd_size; 1815 __le16 flags; 1816 __le16 cookie; 1817 u8 resp_size; 1818 u8 reserved8; 1819 __le64 resp_addr; 1820 __le32 ah_cid; 1821 __le32 unused_0; 1822 }; 1823 1824 /* Initialize Firmware command (112 bytes) */ 1825 struct cmdq_initialize_fw { 1826 u8 opcode; 1827 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL 1828 u8 cmd_size; 1829 __le16 flags; 1830 __le16 cookie; 1831 u8 resp_size; 1832 u8 reserved8; 1833 __le64 resp_addr; 1834 u8 qpc_pg_size_qpc_lvl; 1835 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL 1836 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0 1837 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL 1838 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL 1839 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL 1840 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL 1841 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4 1842 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4) 1843 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4) 1844 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4) 1845 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4) 1846 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4) 1847 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4) 1848 u8 mrw_pg_size_mrw_lvl; 1849 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL 1850 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0 1851 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL 1852 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL 1853 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL 1854 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL 1855 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4 1856 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4) 1857 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4) 1858 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4) 1859 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4) 1860 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4) 1861 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4) 1862 u8 srq_pg_size_srq_lvl; 1863 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL 1864 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0 1865 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL 1866 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL 1867 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL 1868 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL 1869 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4 1870 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 1871 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 1872 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 1873 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 1874 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 1875 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 1876 u8 cq_pg_size_cq_lvl; 1877 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL 1878 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0 1879 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL 1880 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL 1881 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL 1882 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL 1883 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4 1884 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4) 1885 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4) 1886 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4) 1887 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4) 1888 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4) 1889 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4) 1890 u8 tqm_pg_size_tqm_lvl; 1891 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL 1892 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0 1893 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL 1894 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL 1895 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL 1896 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL 1897 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4 1898 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4) 1899 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4) 1900 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4) 1901 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4) 1902 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4) 1903 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4) 1904 u8 tim_pg_size_tim_lvl; 1905 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL 1906 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0 1907 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL 1908 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL 1909 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL 1910 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL 1911 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4 1912 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4) 1913 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4) 1914 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4) 1915 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4) 1916 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4) 1917 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4) 1918 /* This value is (log-base-2-of-DBR-page-size - 12). 1919 * 0 for 4KB. HW supported values are enumerated below. 1920 */ 1921 __le16 log2_dbr_pg_size; 1922 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL 1923 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 1924 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL 1925 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL 1926 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL 1927 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL 1928 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL 1929 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL 1930 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL 1931 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL 1932 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL 1933 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL 1934 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL 1935 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL 1936 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL 1937 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL 1938 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL 1939 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL 1940 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST \ 1941 CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 1942 __le64 qpc_page_dir; 1943 __le64 mrw_page_dir; 1944 __le64 srq_page_dir; 1945 __le64 cq_page_dir; 1946 __le64 tqm_page_dir; 1947 __le64 tim_page_dir; 1948 __le32 number_of_qp; 1949 __le32 number_of_mrw; 1950 __le32 number_of_srq; 1951 __le32 number_of_cq; 1952 __le32 max_qp_per_vf; 1953 __le32 max_mrw_per_vf; 1954 __le32 max_srq_per_vf; 1955 __le32 max_cq_per_vf; 1956 __le32 max_gid_per_vf; 1957 __le32 stat_ctx_id; 1958 }; 1959 1960 /* De-initialize Firmware command (16 bytes) */ 1961 struct cmdq_deinitialize_fw { 1962 u8 opcode; 1963 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL 1964 u8 cmd_size; 1965 __le16 flags; 1966 __le16 cookie; 1967 u8 resp_size; 1968 u8 reserved8; 1969 __le64 resp_addr; 1970 }; 1971 1972 /* Stop function command (16 bytes) */ 1973 struct cmdq_stop_func { 1974 u8 opcode; 1975 #define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC 0x82UL 1976 u8 cmd_size; 1977 __le16 flags; 1978 __le16 cookie; 1979 u8 resp_size; 1980 u8 reserved8; 1981 __le64 resp_addr; 1982 }; 1983 1984 /* Query function command (16 bytes) */ 1985 struct cmdq_query_func { 1986 u8 opcode; 1987 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL 1988 u8 cmd_size; 1989 __le16 flags; 1990 __le16 cookie; 1991 u8 resp_size; 1992 u8 reserved8; 1993 __le64 resp_addr; 1994 }; 1995 1996 /* Set function resources command (16 bytes) */ 1997 struct cmdq_set_func_resources { 1998 u8 opcode; 1999 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL 2000 u8 cmd_size; 2001 __le16 flags; 2002 __le16 cookie; 2003 u8 resp_size; 2004 u8 reserved8; 2005 __le64 resp_addr; 2006 __le32 number_of_qp; 2007 __le32 number_of_mrw; 2008 __le32 number_of_srq; 2009 __le32 number_of_cq; 2010 __le32 max_qp_per_vf; 2011 __le32 max_mrw_per_vf; 2012 __le32 max_srq_per_vf; 2013 __le32 max_cq_per_vf; 2014 __le32 max_gid_per_vf; 2015 __le32 stat_ctx_id; 2016 }; 2017 2018 /* Read hardware resource context command (24 bytes) */ 2019 struct cmdq_read_context { 2020 u8 opcode; 2021 #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT 0x85UL 2022 u8 cmd_size; 2023 __le16 flags; 2024 __le16 cookie; 2025 u8 resp_size; 2026 u8 reserved8; 2027 __le64 resp_addr; 2028 __le32 type_xid; 2029 #define CMDQ_READ_CONTEXT_XID_MASK 0xffffffUL 2030 #define CMDQ_READ_CONTEXT_XID_SFT 0 2031 #define CMDQ_READ_CONTEXT_TYPE_MASK 0xff000000UL 2032 #define CMDQ_READ_CONTEXT_TYPE_SFT 24 2033 #define CMDQ_READ_CONTEXT_TYPE_QPC (0x0UL << 24) 2034 #define CMDQ_READ_CONTEXT_TYPE_CQ (0x1UL << 24) 2035 #define CMDQ_READ_CONTEXT_TYPE_MRW (0x2UL << 24) 2036 #define CMDQ_READ_CONTEXT_TYPE_SRQ (0x3UL << 24) 2037 __le32 unused_0; 2038 }; 2039 2040 /* Map TC to COS. Can only be issued from a PF (24 bytes) */ 2041 struct cmdq_map_tc_to_cos { 2042 u8 opcode; 2043 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL 2044 u8 cmd_size; 2045 __le16 flags; 2046 __le16 cookie; 2047 u8 resp_size; 2048 u8 reserved8; 2049 __le64 resp_addr; 2050 __le16 cos0; 2051 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL 2052 __le16 cos1; 2053 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL 2054 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL 2055 __le32 unused_0; 2056 }; 2057 2058 /* Query version command (16 bytes) */ 2059 struct cmdq_query_version { 2060 u8 opcode; 2061 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL 2062 u8 cmd_size; 2063 __le16 flags; 2064 __le16 cookie; 2065 u8 resp_size; 2066 u8 reserved8; 2067 __le64 resp_addr; 2068 }; 2069 2070 /* Command-Response Event Queue (CREQ) Structures */ 2071 /* Base CREQ Record (16 bytes) */ 2072 struct creq_base { 2073 u8 type; 2074 #define CREQ_BASE_TYPE_MASK 0x3fUL 2075 #define CREQ_BASE_TYPE_SFT 0 2076 #define CREQ_BASE_TYPE_QP_EVENT 0x38UL 2077 #define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL 2078 #define CREQ_BASE_RESERVED2_MASK 0xc0UL 2079 #define CREQ_BASE_RESERVED2_SFT 6 2080 u8 reserved56[7]; 2081 u8 v; 2082 #define CREQ_BASE_V 0x1UL 2083 #define CREQ_BASE_RESERVED7_MASK 0xfeUL 2084 #define CREQ_BASE_RESERVED7_SFT 1 2085 u8 event; 2086 __le16 reserved48[3]; 2087 }; 2088 2089 /* RoCE Function Async Event Notification (16 bytes) */ 2090 struct creq_func_event { 2091 u8 type; 2092 #define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL 2093 #define CREQ_FUNC_EVENT_TYPE_SFT 0 2094 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL 2095 #define CREQ_FUNC_EVENT_RESERVED2_MASK 0xc0UL 2096 #define CREQ_FUNC_EVENT_RESERVED2_SFT 6 2097 u8 reserved56[7]; 2098 u8 v; 2099 #define CREQ_FUNC_EVENT_V 0x1UL 2100 #define CREQ_FUNC_EVENT_RESERVED7_MASK 0xfeUL 2101 #define CREQ_FUNC_EVENT_RESERVED7_SFT 1 2102 u8 event; 2103 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL 2104 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL 2105 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL 2106 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL 2107 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL 2108 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL 2109 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL 2110 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL 2111 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL 2112 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL 2113 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL 2114 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL 2115 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL 2116 __le16 reserved48[3]; 2117 }; 2118 2119 /* RoCE Slowpath Command Completion (16 bytes) */ 2120 struct creq_qp_event { 2121 u8 type; 2122 #define CREQ_QP_EVENT_TYPE_MASK 0x3fUL 2123 #define CREQ_QP_EVENT_TYPE_SFT 0 2124 #define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL 2125 #define CREQ_QP_EVENT_RESERVED2_MASK 0xc0UL 2126 #define CREQ_QP_EVENT_RESERVED2_SFT 6 2127 u8 status; 2128 __le16 cookie; 2129 __le32 reserved32; 2130 u8 v; 2131 #define CREQ_QP_EVENT_V 0x1UL 2132 #define CREQ_QP_EVENT_RESERVED7_MASK 0xfeUL 2133 #define CREQ_QP_EVENT_RESERVED7_SFT 1 2134 u8 event; 2135 #define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL 2136 #define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL 2137 #define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL 2138 #define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL 2139 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL 2140 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL 2141 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL 2142 #define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL 2143 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL 2144 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL 2145 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL 2146 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL 2147 #define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL 2148 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL 2149 #define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL 2150 #define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL 2151 #define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL 2152 #define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL 2153 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL 2154 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL 2155 #define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL 2156 #define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL 2157 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL 2158 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL 2159 #define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL 2160 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL 2161 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL 2162 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL 2163 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL 2164 #define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL 2165 #define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL 2166 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 2167 __le16 reserved48[3]; 2168 }; 2169 2170 /* Create QP command response (16 bytes) */ 2171 struct creq_create_qp_resp { 2172 u8 type; 2173 #define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL 2174 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0 2175 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL 2176 #define CREQ_CREATE_QP_RESP_RESERVED2_MASK 0xc0UL 2177 #define CREQ_CREATE_QP_RESP_RESERVED2_SFT 6 2178 u8 status; 2179 __le16 cookie; 2180 __le32 xid; 2181 u8 v; 2182 #define CREQ_CREATE_QP_RESP_V 0x1UL 2183 #define CREQ_CREATE_QP_RESP_RESERVED7_MASK 0xfeUL 2184 #define CREQ_CREATE_QP_RESP_RESERVED7_SFT 1 2185 u8 event; 2186 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL 2187 __le16 reserved48[3]; 2188 }; 2189 2190 /* Destroy QP command response (16 bytes) */ 2191 struct creq_destroy_qp_resp { 2192 u8 type; 2193 #define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL 2194 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0 2195 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL 2196 #define CREQ_DESTROY_QP_RESP_RESERVED2_MASK 0xc0UL 2197 #define CREQ_DESTROY_QP_RESP_RESERVED2_SFT 6 2198 u8 status; 2199 __le16 cookie; 2200 __le32 xid; 2201 u8 v; 2202 #define CREQ_DESTROY_QP_RESP_V 0x1UL 2203 #define CREQ_DESTROY_QP_RESP_RESERVED7_MASK 0xfeUL 2204 #define CREQ_DESTROY_QP_RESP_RESERVED7_SFT 1 2205 u8 event; 2206 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL 2207 __le16 reserved48[3]; 2208 }; 2209 2210 /* Modify QP command response (16 bytes) */ 2211 struct creq_modify_qp_resp { 2212 u8 type; 2213 #define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL 2214 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0 2215 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL 2216 #define CREQ_MODIFY_QP_RESP_RESERVED2_MASK 0xc0UL 2217 #define CREQ_MODIFY_QP_RESP_RESERVED2_SFT 6 2218 u8 status; 2219 __le16 cookie; 2220 __le32 xid; 2221 u8 v; 2222 #define CREQ_MODIFY_QP_RESP_V 0x1UL 2223 #define CREQ_MODIFY_QP_RESP_RESERVED7_MASK 0xfeUL 2224 #define CREQ_MODIFY_QP_RESP_RESERVED7_SFT 1 2225 u8 event; 2226 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL 2227 __le16 reserved48[3]; 2228 }; 2229 2230 /* cmdq_query_roce_stats (size:128b/16B) */ 2231 struct cmdq_query_roce_stats { 2232 u8 opcode; 2233 #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL 2234 #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST \ 2235 CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 2236 u8 cmd_size; 2237 __le16 flags; 2238 __le16 cookie; 2239 u8 resp_size; 2240 u8 reserved8; 2241 __le64 resp_addr; 2242 }; 2243 2244 /* Query QP command response (16 bytes) */ 2245 struct creq_query_qp_resp { 2246 u8 type; 2247 #define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL 2248 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0 2249 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL 2250 #define CREQ_QUERY_QP_RESP_RESERVED2_MASK 0xc0UL 2251 #define CREQ_QUERY_QP_RESP_RESERVED2_SFT 6 2252 u8 status; 2253 __le16 cookie; 2254 __le32 size; 2255 u8 v; 2256 #define CREQ_QUERY_QP_RESP_V 0x1UL 2257 #define CREQ_QUERY_QP_RESP_RESERVED7_MASK 0xfeUL 2258 #define CREQ_QUERY_QP_RESP_RESERVED7_SFT 1 2259 u8 event; 2260 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL 2261 __le16 reserved48[3]; 2262 }; 2263 2264 /* Query QP command response side buffer structure (104 bytes) */ 2265 struct creq_query_qp_resp_sb { 2266 u8 opcode; 2267 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL 2268 u8 status; 2269 __le16 cookie; 2270 __le16 flags; 2271 u8 resp_size; 2272 u8 reserved8; 2273 __le32 xid; 2274 u8 en_sqd_async_notify_state; 2275 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL 2276 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0 2277 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL 2278 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL 2279 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL 2280 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL 2281 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL 2282 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL 2283 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL 2284 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL 2285 u8 access; 2286 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL 2287 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL 2288 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL 2289 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL 2290 __le16 pkey; 2291 __le32 qkey; 2292 __le32 reserved32; 2293 __le32 dgid[4]; 2294 __le32 flow_label; 2295 __le16 sgid_index; 2296 u8 hop_limit; 2297 u8 traffic_class; 2298 __le16 dest_mac[3]; 2299 __le16 path_mtu_dest_vlan_id; 2300 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL 2301 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0 2302 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL 2303 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12 2304 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12) 2305 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12) 2306 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12) 2307 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12) 2308 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12) 2309 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12) 2310 u8 timeout; 2311 u8 retry_cnt; 2312 u8 rnr_retry; 2313 u8 min_rnr_timer; 2314 __le32 rq_psn; 2315 __le32 sq_psn; 2316 u8 max_rd_atomic; 2317 u8 max_dest_rd_atomic; 2318 u8 tos_dscp_tos_ecn; 2319 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL 2320 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0 2321 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL 2322 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2 2323 u8 enable_cc; 2324 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL 2325 #define CREQ_QUERY_QP_RESP_SB_RESERVED7_MASK 0xfeUL 2326 #define CREQ_QUERY_QP_RESP_SB_RESERVED7_SFT 1 2327 __le32 sq_size; 2328 __le32 rq_size; 2329 __le16 sq_sge; 2330 __le16 rq_sge; 2331 __le32 max_inline_data; 2332 __le32 dest_qp_id; 2333 __le32 unused_1; 2334 __le16 src_mac[3]; 2335 __le16 vlan_pcp_vlan_dei_vlan_id; 2336 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL 2337 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0 2338 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL 2339 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL 2340 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13 2341 }; 2342 2343 /* Create SRQ command response (16 bytes) */ 2344 struct creq_create_srq_resp { 2345 u8 type; 2346 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL 2347 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0 2348 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL 2349 #define CREQ_CREATE_SRQ_RESP_RESERVED2_MASK 0xc0UL 2350 #define CREQ_CREATE_SRQ_RESP_RESERVED2_SFT 6 2351 u8 status; 2352 __le16 cookie; 2353 __le32 xid; 2354 u8 v; 2355 #define CREQ_CREATE_SRQ_RESP_V 0x1UL 2356 #define CREQ_CREATE_SRQ_RESP_RESERVED7_MASK 0xfeUL 2357 #define CREQ_CREATE_SRQ_RESP_RESERVED7_SFT 1 2358 u8 event; 2359 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL 2360 __le16 reserved48[3]; 2361 }; 2362 2363 /* Destroy SRQ command response (16 bytes) */ 2364 struct creq_destroy_srq_resp { 2365 u8 type; 2366 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL 2367 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0 2368 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 2369 #define CREQ_DESTROY_SRQ_RESP_RESERVED2_MASK 0xc0UL 2370 #define CREQ_DESTROY_SRQ_RESP_RESERVED2_SFT 6 2371 u8 status; 2372 __le16 cookie; 2373 __le32 xid; 2374 u8 v; 2375 #define CREQ_DESTROY_SRQ_RESP_V 0x1UL 2376 #define CREQ_DESTROY_SRQ_RESP_RESERVED7_MASK 0xfeUL 2377 #define CREQ_DESTROY_SRQ_RESP_RESERVED7_SFT 1 2378 u8 event; 2379 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL 2380 __le16 enable_for_arm[3]; 2381 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL 2382 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 2383 #define CREQ_DESTROY_SRQ_RESP_RESERVED46_MASK 0xfffc0000UL 2384 #define CREQ_DESTROY_SRQ_RESP_RESERVED46_SFT 18 2385 }; 2386 2387 /* Query SRQ command response (16 bytes) */ 2388 struct creq_query_srq_resp { 2389 u8 type; 2390 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL 2391 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0 2392 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 2393 #define CREQ_QUERY_SRQ_RESP_RESERVED2_MASK 0xc0UL 2394 #define CREQ_QUERY_SRQ_RESP_RESERVED2_SFT 6 2395 u8 status; 2396 __le16 cookie; 2397 __le32 size; 2398 u8 v; 2399 #define CREQ_QUERY_SRQ_RESP_V 0x1UL 2400 #define CREQ_QUERY_SRQ_RESP_RESERVED7_MASK 0xfeUL 2401 #define CREQ_QUERY_SRQ_RESP_RESERVED7_SFT 1 2402 u8 event; 2403 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL 2404 __le16 reserved48[3]; 2405 }; 2406 2407 /* Query SRQ command response side buffer structure (24 bytes) */ 2408 struct creq_query_srq_resp_sb { 2409 u8 opcode; 2410 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL 2411 u8 status; 2412 __le16 cookie; 2413 __le16 flags; 2414 u8 resp_size; 2415 u8 reserved8; 2416 __le32 xid; 2417 __le16 srq_limit; 2418 __le16 reserved16; 2419 __le32 data[4]; 2420 }; 2421 2422 /* Create CQ command Response (16 bytes) */ 2423 struct creq_create_cq_resp { 2424 u8 type; 2425 #define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL 2426 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0 2427 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL 2428 #define CREQ_CREATE_CQ_RESP_RESERVED2_MASK 0xc0UL 2429 #define CREQ_CREATE_CQ_RESP_RESERVED2_SFT 6 2430 u8 status; 2431 __le16 cookie; 2432 __le32 xid; 2433 u8 v; 2434 #define CREQ_CREATE_CQ_RESP_V 0x1UL 2435 #define CREQ_CREATE_CQ_RESP_RESERVED7_MASK 0xfeUL 2436 #define CREQ_CREATE_CQ_RESP_RESERVED7_SFT 1 2437 u8 event; 2438 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL 2439 __le16 reserved48[3]; 2440 }; 2441 2442 /* Destroy CQ command response (16 bytes) */ 2443 struct creq_destroy_cq_resp { 2444 u8 type; 2445 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL 2446 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0 2447 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL 2448 #define CREQ_DESTROY_CQ_RESP_RESERVED2_MASK 0xc0UL 2449 #define CREQ_DESTROY_CQ_RESP_RESERVED2_SFT 6 2450 u8 status; 2451 __le16 cookie; 2452 __le32 xid; 2453 u8 v; 2454 #define CREQ_DESTROY_CQ_RESP_V 0x1UL 2455 #define CREQ_DESTROY_CQ_RESP_RESERVED7_MASK 0xfeUL 2456 #define CREQ_DESTROY_CQ_RESP_RESERVED7_SFT 1 2457 u8 event; 2458 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL 2459 __le16 cq_arm_lvl; 2460 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL 2461 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 2462 #define CREQ_DESTROY_CQ_RESP_RESERVED14_MASK 0xfffcUL 2463 #define CREQ_DESTROY_CQ_RESP_RESERVED14_SFT 2 2464 __le16 total_cnq_events; 2465 __le16 reserved16; 2466 }; 2467 2468 /* Resize CQ command response (16 bytes) */ 2469 struct creq_resize_cq_resp { 2470 u8 type; 2471 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL 2472 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0 2473 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL 2474 #define CREQ_RESIZE_CQ_RESP_RESERVED2_MASK 0xc0UL 2475 #define CREQ_RESIZE_CQ_RESP_RESERVED2_SFT 6 2476 u8 status; 2477 __le16 cookie; 2478 __le32 xid; 2479 u8 v; 2480 #define CREQ_RESIZE_CQ_RESP_V 0x1UL 2481 #define CREQ_RESIZE_CQ_RESP_RESERVED7_MASK 0xfeUL 2482 #define CREQ_RESIZE_CQ_RESP_RESERVED7_SFT 1 2483 u8 event; 2484 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL 2485 __le16 reserved48[3]; 2486 }; 2487 2488 /* Allocate MRW command response (16 bytes) */ 2489 struct creq_allocate_mrw_resp { 2490 u8 type; 2491 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL 2492 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0 2493 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL 2494 #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_MASK 0xc0UL 2495 #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_SFT 6 2496 u8 status; 2497 __le16 cookie; 2498 __le32 xid; 2499 u8 v; 2500 #define CREQ_ALLOCATE_MRW_RESP_V 0x1UL 2501 #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_MASK 0xfeUL 2502 #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_SFT 1 2503 u8 event; 2504 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL 2505 __le16 reserved48[3]; 2506 }; 2507 2508 /* De-allocate key command response (16 bytes) */ 2509 struct creq_deallocate_key_resp { 2510 u8 type; 2511 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL 2512 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0 2513 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL 2514 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_MASK 0xc0UL 2515 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_SFT 6 2516 u8 status; 2517 __le16 cookie; 2518 __le32 xid; 2519 u8 v; 2520 #define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL 2521 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_MASK 0xfeUL 2522 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_SFT 1 2523 u8 event; 2524 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL 2525 __le16 reserved16; 2526 __le32 bound_window_info; 2527 }; 2528 2529 /* Register MR command response (16 bytes) */ 2530 struct creq_register_mr_resp { 2531 u8 type; 2532 #define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL 2533 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0 2534 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 2535 #define CREQ_REGISTER_MR_RESP_RESERVED2_MASK 0xc0UL 2536 #define CREQ_REGISTER_MR_RESP_RESERVED2_SFT 6 2537 u8 status; 2538 __le16 cookie; 2539 __le32 xid; 2540 u8 v; 2541 #define CREQ_REGISTER_MR_RESP_V 0x1UL 2542 #define CREQ_REGISTER_MR_RESP_RESERVED7_MASK 0xfeUL 2543 #define CREQ_REGISTER_MR_RESP_RESERVED7_SFT 1 2544 u8 event; 2545 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL 2546 __le16 reserved48[3]; 2547 }; 2548 2549 /* Deregister MR command response (16 bytes) */ 2550 struct creq_deregister_mr_resp { 2551 u8 type; 2552 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL 2553 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0 2554 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 2555 #define CREQ_DEREGISTER_MR_RESP_RESERVED2_MASK 0xc0UL 2556 #define CREQ_DEREGISTER_MR_RESP_RESERVED2_SFT 6 2557 u8 status; 2558 __le16 cookie; 2559 __le32 xid; 2560 u8 v; 2561 #define CREQ_DEREGISTER_MR_RESP_V 0x1UL 2562 #define CREQ_DEREGISTER_MR_RESP_RESERVED7_MASK 0xfeUL 2563 #define CREQ_DEREGISTER_MR_RESP_RESERVED7_SFT 1 2564 u8 event; 2565 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL 2566 __le16 reserved16; 2567 __le32 bound_windows; 2568 }; 2569 2570 /* Add GID command response (16 bytes) */ 2571 struct creq_add_gid_resp { 2572 u8 type; 2573 #define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL 2574 #define CREQ_ADD_GID_RESP_TYPE_SFT 0 2575 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL 2576 #define CREQ_ADD_GID_RESP_RESERVED2_MASK 0xc0UL 2577 #define CREQ_ADD_GID_RESP_RESERVED2_SFT 6 2578 u8 status; 2579 __le16 cookie; 2580 __le32 xid; 2581 u8 v; 2582 #define CREQ_ADD_GID_RESP_V 0x1UL 2583 #define CREQ_ADD_GID_RESP_RESERVED7_MASK 0xfeUL 2584 #define CREQ_ADD_GID_RESP_RESERVED7_SFT 1 2585 u8 event; 2586 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL 2587 __le16 reserved48[3]; 2588 }; 2589 2590 /* Delete GID command response (16 bytes) */ 2591 struct creq_delete_gid_resp { 2592 u8 type; 2593 #define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL 2594 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0 2595 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL 2596 #define CREQ_DELETE_GID_RESP_RESERVED2_MASK 0xc0UL 2597 #define CREQ_DELETE_GID_RESP_RESERVED2_SFT 6 2598 u8 status; 2599 __le16 cookie; 2600 __le32 xid; 2601 u8 v; 2602 #define CREQ_DELETE_GID_RESP_V 0x1UL 2603 #define CREQ_DELETE_GID_RESP_RESERVED7_MASK 0xfeUL 2604 #define CREQ_DELETE_GID_RESP_RESERVED7_SFT 1 2605 u8 event; 2606 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL 2607 __le16 reserved48[3]; 2608 }; 2609 2610 /* Modify GID command response (16 bytes) */ 2611 struct creq_modify_gid_resp { 2612 u8 type; 2613 #define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL 2614 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0 2615 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL 2616 #define CREQ_MODIFY_GID_RESP_RESERVED2_MASK 0xc0UL 2617 #define CREQ_MODIFY_GID_RESP_RESERVED2_SFT 6 2618 u8 status; 2619 __le16 cookie; 2620 __le32 xid; 2621 u8 v; 2622 #define CREQ_MODIFY_GID_RESP_V 0x1UL 2623 #define CREQ_MODIFY_GID_RESP_RESERVED7_MASK 0xfeUL 2624 #define CREQ_MODIFY_GID_RESP_RESERVED7_SFT 1 2625 u8 event; 2626 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL 2627 __le16 reserved48[3]; 2628 }; 2629 2630 /* Query GID command response (16 bytes) */ 2631 struct creq_query_gid_resp { 2632 u8 type; 2633 #define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL 2634 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0 2635 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL 2636 #define CREQ_QUERY_GID_RESP_RESERVED2_MASK 0xc0UL 2637 #define CREQ_QUERY_GID_RESP_RESERVED2_SFT 6 2638 u8 status; 2639 __le16 cookie; 2640 __le32 size; 2641 u8 v; 2642 #define CREQ_QUERY_GID_RESP_V 0x1UL 2643 #define CREQ_QUERY_GID_RESP_RESERVED7_MASK 0xfeUL 2644 #define CREQ_QUERY_GID_RESP_RESERVED7_SFT 1 2645 u8 event; 2646 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL 2647 __le16 reserved48[3]; 2648 }; 2649 2650 /* Query GID command response side buffer structure (40 bytes) */ 2651 struct creq_query_gid_resp_sb { 2652 u8 opcode; 2653 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL 2654 u8 status; 2655 __le16 cookie; 2656 __le16 flags; 2657 u8 resp_size; 2658 u8 reserved8; 2659 __le32 gid[4]; 2660 __le16 src_mac[3]; 2661 __le16 vlan; 2662 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL 2663 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0 2664 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL 2665 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12 2666 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12) 2667 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12) 2668 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12) 2669 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12) 2670 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12) 2671 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 2672 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 2673 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 2674 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST \ 2675 CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 2676 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL 2677 __le16 ipid; 2678 __le16 gid_index; 2679 __le32 unused_0; 2680 }; 2681 2682 /* Create QP1 command response (16 bytes) */ 2683 struct creq_create_qp1_resp { 2684 u8 type; 2685 #define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL 2686 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0 2687 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL 2688 #define CREQ_CREATE_QP1_RESP_RESERVED2_MASK 0xc0UL 2689 #define CREQ_CREATE_QP1_RESP_RESERVED2_SFT 6 2690 u8 status; 2691 __le16 cookie; 2692 __le32 xid; 2693 u8 v; 2694 #define CREQ_CREATE_QP1_RESP_V 0x1UL 2695 #define CREQ_CREATE_QP1_RESP_RESERVED7_MASK 0xfeUL 2696 #define CREQ_CREATE_QP1_RESP_RESERVED7_SFT 1 2697 u8 event; 2698 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL 2699 __le16 reserved48[3]; 2700 }; 2701 2702 /* Destroy QP1 command response (16 bytes) */ 2703 struct creq_destroy_qp1_resp { 2704 u8 type; 2705 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL 2706 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0 2707 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL 2708 #define CREQ_DESTROY_QP1_RESP_RESERVED2_MASK 0xc0UL 2709 #define CREQ_DESTROY_QP1_RESP_RESERVED2_SFT 6 2710 u8 status; 2711 __le16 cookie; 2712 __le32 xid; 2713 u8 v; 2714 #define CREQ_DESTROY_QP1_RESP_V 0x1UL 2715 #define CREQ_DESTROY_QP1_RESP_RESERVED7_MASK 0xfeUL 2716 #define CREQ_DESTROY_QP1_RESP_RESERVED7_SFT 1 2717 u8 event; 2718 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL 2719 __le16 reserved48[3]; 2720 }; 2721 2722 /* Create AH command response (16 bytes) */ 2723 struct creq_create_ah_resp { 2724 u8 type; 2725 #define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL 2726 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0 2727 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL 2728 #define CREQ_CREATE_AH_RESP_RESERVED2_MASK 0xc0UL 2729 #define CREQ_CREATE_AH_RESP_RESERVED2_SFT 6 2730 u8 status; 2731 __le16 cookie; 2732 __le32 xid; 2733 u8 v; 2734 #define CREQ_CREATE_AH_RESP_V 0x1UL 2735 #define CREQ_CREATE_AH_RESP_RESERVED7_MASK 0xfeUL 2736 #define CREQ_CREATE_AH_RESP_RESERVED7_SFT 1 2737 u8 event; 2738 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL 2739 __le16 reserved48[3]; 2740 }; 2741 2742 /* Destroy AH command response (16 bytes) */ 2743 struct creq_destroy_ah_resp { 2744 u8 type; 2745 #define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL 2746 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0 2747 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL 2748 #define CREQ_DESTROY_AH_RESP_RESERVED2_MASK 0xc0UL 2749 #define CREQ_DESTROY_AH_RESP_RESERVED2_SFT 6 2750 u8 status; 2751 __le16 cookie; 2752 __le32 xid; 2753 u8 v; 2754 #define CREQ_DESTROY_AH_RESP_V 0x1UL 2755 #define CREQ_DESTROY_AH_RESP_RESERVED7_MASK 0xfeUL 2756 #define CREQ_DESTROY_AH_RESP_RESERVED7_SFT 1 2757 u8 event; 2758 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL 2759 __le16 reserved48[3]; 2760 }; 2761 2762 /* Initialize Firmware command response (16 bytes) */ 2763 struct creq_initialize_fw_resp { 2764 u8 type; 2765 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 2766 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0 2767 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 2768 #define CREQ_INITIALIZE_FW_RESP_RESERVED2_MASK 0xc0UL 2769 #define CREQ_INITIALIZE_FW_RESP_RESERVED2_SFT 6 2770 u8 status; 2771 __le16 cookie; 2772 __le32 reserved32; 2773 u8 v; 2774 #define CREQ_INITIALIZE_FW_RESP_V 0x1UL 2775 #define CREQ_INITIALIZE_FW_RESP_RESERVED7_MASK 0xfeUL 2776 #define CREQ_INITIALIZE_FW_RESP_RESERVED7_SFT 1 2777 u8 event; 2778 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL 2779 __le16 reserved48[3]; 2780 }; 2781 2782 /* De-initialize Firmware command response (16 bytes) */ 2783 struct creq_deinitialize_fw_resp { 2784 u8 type; 2785 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 2786 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0 2787 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 2788 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_MASK 0xc0UL 2789 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_SFT 6 2790 u8 status; 2791 __le16 cookie; 2792 __le32 reserved32; 2793 u8 v; 2794 #define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL 2795 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_MASK 0xfeUL 2796 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_SFT 1 2797 u8 event; 2798 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL 2799 __le16 reserved48[3]; 2800 }; 2801 2802 /* Stop function command response (16 bytes) */ 2803 struct creq_stop_func_resp { 2804 u8 type; 2805 #define CREQ_STOP_FUNC_RESP_TYPE_MASK 0x3fUL 2806 #define CREQ_STOP_FUNC_RESP_TYPE_SFT 0 2807 #define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT 0x38UL 2808 #define CREQ_STOP_FUNC_RESP_RESERVED2_MASK 0xc0UL 2809 #define CREQ_STOP_FUNC_RESP_RESERVED2_SFT 6 2810 u8 status; 2811 __le16 cookie; 2812 __le32 reserved32; 2813 u8 v; 2814 #define CREQ_STOP_FUNC_RESP_V 0x1UL 2815 #define CREQ_STOP_FUNC_RESP_RESERVED7_MASK 0xfeUL 2816 #define CREQ_STOP_FUNC_RESP_RESERVED7_SFT 1 2817 u8 event; 2818 #define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC 0x82UL 2819 __le16 reserved48[3]; 2820 }; 2821 2822 /* Query function command response (16 bytes) */ 2823 struct creq_query_func_resp { 2824 u8 type; 2825 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL 2826 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0 2827 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL 2828 #define CREQ_QUERY_FUNC_RESP_RESERVED2_MASK 0xc0UL 2829 #define CREQ_QUERY_FUNC_RESP_RESERVED2_SFT 6 2830 u8 status; 2831 __le16 cookie; 2832 __le32 size; 2833 u8 v; 2834 #define CREQ_QUERY_FUNC_RESP_V 0x1UL 2835 #define CREQ_QUERY_FUNC_RESP_RESERVED7_MASK 0xfeUL 2836 #define CREQ_QUERY_FUNC_RESP_RESERVED7_SFT 1 2837 u8 event; 2838 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL 2839 __le16 reserved48[3]; 2840 }; 2841 2842 /* Query function command response side buffer structure (88 bytes) */ 2843 struct creq_query_func_resp_sb { 2844 u8 opcode; 2845 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL 2846 u8 status; 2847 __le16 cookie; 2848 __le16 flags; 2849 u8 resp_size; 2850 u8 reserved8; 2851 __le64 max_mr_size; 2852 __le32 max_qp; 2853 __le16 max_qp_wr; 2854 __le16 dev_cap_flags; 2855 #define CREQ_QUERY_FUNC_RESP_SB_DEV_CAP_FLAGS_RESIZE_QP 0x1UL 2856 #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL 2857 __le32 max_cq; 2858 __le32 max_cqe; 2859 __le32 max_pd; 2860 u8 max_sge; 2861 u8 max_srq_sge; 2862 u8 max_qp_rd_atom; 2863 u8 max_qp_init_rd_atom; 2864 __le32 max_mr; 2865 __le32 max_mw; 2866 __le32 max_raw_eth_qp; 2867 __le32 max_ah; 2868 __le32 max_fmr; 2869 __le32 max_srq_wr; 2870 __le32 max_pkeys; 2871 __le32 max_inline_data; 2872 u8 max_map_per_fmr; 2873 u8 l2_db_space_size; 2874 __le16 max_srq; 2875 __le32 max_gid; 2876 __le32 tqm_alloc_reqs[12]; 2877 __le32 max_dpi; 2878 __le32 reserved_32; 2879 }; 2880 2881 /* Set resources command response (16 bytes) */ 2882 struct creq_set_func_resources_resp { 2883 u8 type; 2884 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL 2885 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0 2886 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL 2887 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_MASK 0xc0UL 2888 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_SFT 6 2889 u8 status; 2890 __le16 cookie; 2891 __le32 reserved32; 2892 u8 v; 2893 #define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL 2894 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_MASK 0xfeUL 2895 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_SFT 1 2896 u8 event; 2897 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL 2898 __le16 reserved48[3]; 2899 }; 2900 2901 /* Map TC to COS response (16 bytes) */ 2902 struct creq_map_tc_to_cos_resp { 2903 u8 type; 2904 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL 2905 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0 2906 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL 2907 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_MASK 0xc0UL 2908 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_SFT 6 2909 u8 status; 2910 __le16 cookie; 2911 __le32 reserved32; 2912 u8 v; 2913 #define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL 2914 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_MASK 0xfeUL 2915 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_SFT 1 2916 u8 event; 2917 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL 2918 __le16 reserved48[3]; 2919 }; 2920 2921 /* Query version response (16 bytes) */ 2922 struct creq_query_version_resp { 2923 u8 type; 2924 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL 2925 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0 2926 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL 2927 #define CREQ_QUERY_VERSION_RESP_RESERVED2_MASK 0xc0UL 2928 #define CREQ_QUERY_VERSION_RESP_RESERVED2_SFT 6 2929 u8 status; 2930 __le16 cookie; 2931 u8 fw_maj; 2932 u8 fw_minor; 2933 u8 fw_bld; 2934 u8 fw_rsvd; 2935 u8 v; 2936 #define CREQ_QUERY_VERSION_RESP_V 0x1UL 2937 #define CREQ_QUERY_VERSION_RESP_RESERVED7_MASK 0xfeUL 2938 #define CREQ_QUERY_VERSION_RESP_RESERVED7_SFT 1 2939 u8 event; 2940 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL 2941 __le16 reserved16; 2942 u8 intf_maj; 2943 u8 intf_minor; 2944 u8 intf_bld; 2945 u8 intf_rsvd; 2946 }; 2947 2948 /* Modify congestion control command response (16 bytes) */ 2949 struct creq_modify_cc_resp { 2950 u8 type; 2951 #define CREQ_MODIFY_CC_RESP_TYPE_MASK 0x3fUL 2952 #define CREQ_MODIFY_CC_RESP_TYPE_SFT 0 2953 #define CREQ_MODIFY_CC_RESP_TYPE_QP_EVENT 0x38UL 2954 #define CREQ_MODIFY_CC_RESP_RESERVED2_MASK 0xc0UL 2955 #define CREQ_MODIFY_CC_RESP_RESERVED2_SFT 6 2956 u8 status; 2957 __le16 cookie; 2958 __le32 reserved32; 2959 u8 v; 2960 #define CREQ_MODIFY_CC_RESP_V 0x1UL 2961 #define CREQ_MODIFY_CC_RESP_RESERVED7_MASK 0xfeUL 2962 #define CREQ_MODIFY_CC_RESP_RESERVED7_SFT 1 2963 u8 event; 2964 #define CREQ_MODIFY_CC_RESP_EVENT_MODIFY_CC 0x8cUL 2965 __le16 reserved48[3]; 2966 }; 2967 2968 /* Query congestion control command response (16 bytes) */ 2969 struct creq_query_cc_resp { 2970 u8 type; 2971 #define CREQ_QUERY_CC_RESP_TYPE_MASK 0x3fUL 2972 #define CREQ_QUERY_CC_RESP_TYPE_SFT 0 2973 #define CREQ_QUERY_CC_RESP_TYPE_QP_EVENT 0x38UL 2974 #define CREQ_QUERY_CC_RESP_RESERVED2_MASK 0xc0UL 2975 #define CREQ_QUERY_CC_RESP_RESERVED2_SFT 6 2976 u8 status; 2977 __le16 cookie; 2978 __le32 size; 2979 u8 v; 2980 #define CREQ_QUERY_CC_RESP_V 0x1UL 2981 #define CREQ_QUERY_CC_RESP_RESERVED7_MASK 0xfeUL 2982 #define CREQ_QUERY_CC_RESP_RESERVED7_SFT 1 2983 u8 event; 2984 #define CREQ_QUERY_CC_RESP_EVENT_QUERY_CC 0x8dUL 2985 __le16 reserved48[3]; 2986 }; 2987 2988 /* Query congestion control command response side buffer structure (32 bytes) */ 2989 struct creq_query_cc_resp_sb { 2990 u8 opcode; 2991 #define CREQ_QUERY_CC_RESP_SB_OPCODE_QUERY_CC 0x8dUL 2992 u8 status; 2993 __le16 cookie; 2994 __le16 flags; 2995 u8 resp_size; 2996 u8 reserved8; 2997 u8 enable_cc; 2998 #define CREQ_QUERY_CC_RESP_SB_ENABLE_CC 0x1UL 2999 u8 g; 3000 #define CREQ_QUERY_CC_RESP_SB_G_MASK 0x7UL 3001 #define CREQ_QUERY_CC_RESP_SB_G_SFT 0 3002 u8 num_phases_per_state; 3003 __le16 init_cr; 3004 u8 unused_2; 3005 __le16 unused_3; 3006 u8 unused_4; 3007 __le16 init_tr; 3008 u8 tos_dscp_tos_ecn; 3009 #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_MASK 0x3UL 3010 #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_SFT 0 3011 #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL 3012 #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_SFT 2 3013 __le64 reserved64; 3014 __le64 reserved64_1; 3015 }; 3016 3017 /* creq_query_roce_stats_resp (size:128b/16B) */ 3018 struct creq_query_roce_stats_resp { 3019 u8 type; 3020 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL 3021 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0 3022 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL 3023 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST \ 3024 CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 3025 u8 status; 3026 __le16 cookie; 3027 __le32 size; 3028 u8 v; 3029 #define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL 3030 u8 event; 3031 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL 3032 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST \ 3033 CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 3034 u8 reserved48[6]; 3035 }; 3036 3037 /* creq_query_roce_stats_resp_sb (size:2624b/328B) */ 3038 struct creq_query_roce_stats_resp_sb { 3039 u8 opcode; 3040 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL 3041 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \ 3042 CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 3043 u8 status; 3044 __le16 cookie; 3045 __le16 flags; 3046 u8 resp_size; 3047 u8 rsvd; 3048 __le32 num_counters; 3049 __le32 rsvd1; 3050 __le64 to_retransmits; 3051 __le64 seq_err_naks_rcvd; 3052 __le64 max_retry_exceeded; 3053 __le64 rnr_naks_rcvd; 3054 __le64 missing_resp; 3055 __le64 unrecoverable_err; 3056 __le64 bad_resp_err; 3057 __le64 local_qp_op_err; 3058 __le64 local_protection_err; 3059 __le64 mem_mgmt_op_err; 3060 __le64 remote_invalid_req_err; 3061 __le64 remote_access_err; 3062 __le64 remote_op_err; 3063 __le64 dup_req; 3064 __le64 res_exceed_max; 3065 __le64 res_length_mismatch; 3066 __le64 res_exceeds_wqe; 3067 __le64 res_opcode_err; 3068 __le64 res_rx_invalid_rkey; 3069 __le64 res_rx_domain_err; 3070 __le64 res_rx_no_perm; 3071 __le64 res_rx_range_err; 3072 __le64 res_tx_invalid_rkey; 3073 __le64 res_tx_domain_err; 3074 __le64 res_tx_no_perm; 3075 __le64 res_tx_range_err; 3076 __le64 res_irrq_oflow; 3077 __le64 res_unsup_opcode; 3078 __le64 res_unaligned_atomic; 3079 __le64 res_rem_inv_err; 3080 __le64 res_mem_error; 3081 __le64 res_srq_err; 3082 __le64 res_cmp_err; 3083 __le64 res_invalid_dup_rkey; 3084 __le64 res_wqe_format_err; 3085 __le64 res_cq_load_err; 3086 __le64 res_srq_load_err; 3087 __le64 res_tx_pci_err; 3088 __le64 res_rx_pci_err; 3089 __le64 res_oos_drop_count; 3090 __le64 active_qp_count_p0; 3091 __le64 active_qp_count_p1; 3092 __le64 active_qp_count_p2; 3093 __le64 active_qp_count_p3; 3094 }; 3095 3096 /* cmdq_query_roce_stats_ext (size:192b/24B) */ 3097 struct cmdq_query_roce_stats_ext { 3098 u8 opcode; 3099 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL 3100 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST \ 3101 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 3102 u8 cmd_size; 3103 __le16 flags; 3104 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL 3105 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL 3106 __le16 cookie; 3107 u8 resp_size; 3108 u8 collection_id; 3109 __le64 resp_addr; 3110 __le32 function_id; 3111 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL 3112 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0 3113 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL 3114 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8 3115 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL 3116 __le32 reserved32; 3117 }; 3118 3119 /* creq_query_roce_stats_ext_resp (size:128b/16B) */ 3120 struct creq_query_roce_stats_ext_resp { 3121 u8 type; 3122 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL 3123 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0 3124 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL 3125 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST \ 3126 CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 3127 u8 status; 3128 __le16 cookie; 3129 __le32 size; 3130 u8 v; 3131 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL 3132 u8 event; 3133 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL 3134 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST \ 3135 CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 3136 u8 reserved48[6]; 3137 }; 3138 3139 /* creq_query_roce_stats_ext_resp_sb (size:1536b/192B) */ 3140 struct creq_query_roce_stats_ext_resp_sb { 3141 u8 opcode; 3142 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 3143 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST \ 3144 CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 3145 u8 status; 3146 __le16 cookie; 3147 __le16 flags; 3148 u8 resp_size; 3149 u8 rsvd; 3150 __le64 tx_atomic_req_pkts; 3151 __le64 tx_read_req_pkts; 3152 __le64 tx_read_res_pkts; 3153 __le64 tx_write_req_pkts; 3154 __le64 tx_send_req_pkts; 3155 __le64 tx_roce_pkts; 3156 __le64 tx_roce_bytes; 3157 __le64 rx_atomic_req_pkts; 3158 __le64 rx_read_req_pkts; 3159 __le64 rx_read_res_pkts; 3160 __le64 rx_write_req_pkts; 3161 __le64 rx_send_req_pkts; 3162 __le64 rx_roce_pkts; 3163 __le64 rx_roce_bytes; 3164 __le64 rx_roce_good_pkts; 3165 __le64 rx_roce_good_bytes; 3166 __le64 rx_out_of_buffer_pkts; 3167 __le64 rx_out_of_sequence_pkts; 3168 __le64 tx_cnp_pkts; 3169 __le64 rx_cnp_pkts; 3170 __le64 rx_ecn_marked_pkts; 3171 __le64 tx_cnp_bytes; 3172 __le64 rx_cnp_bytes; 3173 }; 3174 3175 /* QP error notification event (16 bytes) */ 3176 struct creq_qp_error_notification { 3177 u8 type; 3178 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 3179 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0 3180 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL 3181 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_MASK 0xc0UL 3182 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_SFT 6 3183 u8 status; 3184 u8 req_slow_path_state; 3185 u8 req_err_state_reason; 3186 __le32 xid; 3187 u8 v; 3188 #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL 3189 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_MASK 0xfeUL 3190 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_SFT 1 3191 u8 event; 3192 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 3193 u8 res_slow_path_state; 3194 u8 res_err_state_reason; 3195 __le16 sq_cons_idx; 3196 __le16 rq_cons_idx; 3197 }; 3198 3199 /* RoCE Slowpath HSI Specification 1.6.0 */ 3200 #define ROCE_SP_HSI_VERSION_MAJOR 1 3201 #define ROCE_SP_HSI_VERSION_MINOR 6 3202 #define ROCE_SP_HSI_VERSION_UPDATE 0 3203 3204 #define ROCE_SP_HSI_VERSION_STR "1.6.0" 3205 /* 3206 * Following is the signature for ROCE_SP_HSI message field that indicates not 3207 * applicable (All F's). Need to cast it the size of the field if needed. 3208 */ 3209 #define ROCE_SP_HSI_NA_SIGNATURE ((__le32)(-1)) 3210 #endif /* __BNXT_RE_HSI_H__ */ 3211