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Searched refs:CLR_BIT (Results 1 – 5 of 5) sorted by relevance

/linux-5.19.10/drivers/scsi/sym53c8xx_2/
Dsym_nvram.c236 #define CLR_BIT 1 macro
251 case CLR_BIT: in S24C16_set_bit()
274 S24C16_set_bit(np, 0, gpreg, CLR_BIT); in S24C16_start()
299 S24C16_set_bit(np, 0, gpreg, CLR_BIT); in S24C16_do_bit()
384 S24C16_set_bit(np, 0, &gpreg, CLR_BIT); in sym_write_S24C16_nvram()
438 S24C16_set_bit(np, 0, &gpreg, CLR_BIT); in sym_read_S24C16_nvram()
489 #undef CLR_BIT
/linux-5.19.10/drivers/usb/storage/
Drealtek_cr.c121 #define CLR_BIT(data, idx) ((data) &= ~(1 << (idx))) macro
572 CLR_BIT(value, 0); in config_autodelink_after_power_on()
573 CLR_BIT(value, 1); in config_autodelink_after_power_on()
577 CLR_BIT(value, 2); in config_autodelink_after_power_on()
595 CLR_BIT(value, 2); in config_autodelink_after_power_on()
599 CLR_BIT(value, 0); in config_autodelink_after_power_on()
600 CLR_BIT(value, 7); in config_autodelink_after_power_on()
/linux-5.19.10/drivers/crypto/qat/qat_common/
Dqat_hal.c153 #define CLR_BIT(wrd, bit) ((wrd) & ~(1 << (bit))) macro
171 CLR_BIT(csr, CE_INUSE_CONTEXTS_BITPOS); in qat_hal_set_ae_ctx_mode()
186 CLR_BIT(csr, CE_NN_MODE_BITPOS); in qat_hal_set_ae_nn_mode()
206 CLR_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS); in qat_hal_set_ae_lm_mode()
211 CLR_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS); in qat_hal_set_ae_lm_mode()
216 CLR_BIT(csr, CE_LMADDR_2_GLOBAL_BITPOS); in qat_hal_set_ae_lm_mode()
221 CLR_BIT(csr, CE_LMADDR_3_GLOBAL_BITPOS); in qat_hal_set_ae_lm_mode()
242 CLR_BIT(csr, CE_T_INDEX_GLOBAL_BITPOS); in qat_hal_set_ae_tindex_mode()
1069 newcsr_val = CLR_BIT(csr_val, MMC_SHARE_CS_BITPOS); in qat_hal_exec_micro_inst()
/linux-5.19.10/drivers/staging/rts5208/
Drtsx_card.c565 CLR_BIT(chip->lun_mc, chip->card2lun[SD_CARD]); in rtsx_init_cards()
578 CLR_BIT(chip->lun_mc, chip->card2lun[XD_CARD]); in rtsx_init_cards()
594 CLR_BIT(chip->lun_mc, chip->card2lun[MS_CARD]); in rtsx_init_cards()
Drtsx_chip.h326 #define CLR_BIT(data, idx) ((data) &= ~(1 << (idx))) macro