| /linux-5.19.10/include/dt-bindings/clock/ |
| D | exynos5410.h | 38 #define CLK_UART2 259 macro
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| D | actions,s500-cmu.h | 60 #define CLK_UART2 40 macro
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| D | actions,s700-cmu.h | 60 #define CLK_UART2 38 macro
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| D | actions,s900-cmu.h | 87 #define CLK_UART2 69 macro
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| D | exynos5250.h | 95 #define CLK_UART2 291 macro
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| D | s5pv210.h | 159 #define CLK_UART2 141 macro
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| D | exynos4.h | 152 #define CLK_UART2 314 macro
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| D | exynos5420.h | 68 #define CLK_UART2 259 macro
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| D | exynos3250.h | 228 #define CLK_UART2 222 macro
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| D | sprd,sc9860-clk.h | 87 #define CLK_UART2 4 macro
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| /linux-5.19.10/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 199 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
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| D | clk-s5pv210.c | 574 GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
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| D | clk-exynos5250.c | 575 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
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| D | clk-exynos3250.c | 663 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
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| D | clk-exynos4.c | 852 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
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| /linux-5.19.10/arch/arm64/boot/dts/actions/ |
| D | s700.dtsi | 135 clocks = <&cmu CLK_UART2>;
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| D | s900.dtsi | 141 clocks = <&cmu CLK_UART2>;
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| /linux-5.19.10/arch/arm/boot/dts/ |
| D | s5pv210.dtsi | 343 clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>,
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| D | owl-s500.dtsi | 152 clocks = <&cmu CLK_UART2>;
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| D | exynos5410.dtsi | 354 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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| /linux-5.19.10/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 102 <&ap_clk CLK_UART2>, <&ext_26m>;
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| /linux-5.19.10/drivers/clk/actions/ |
| D | owl-s500.c | 491 [CLK_UART2] = &uart2_clk.common.hw,
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| D | owl-s700.c | 530 [CLK_UART2] = &clk_uart2.common.hw,
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| D | owl-s900.c | 678 [CLK_UART2] = &uart2_clk.common.hw,
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| /linux-5.19.10/drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 308 D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
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