| /linux-5.19.10/include/dt-bindings/clock/ |
| D | exynos5410.h | 37 #define CLK_UART1 258 macro
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| D | actions,s500-cmu.h | 59 #define CLK_UART1 39 macro
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| D | actions,s700-cmu.h | 59 #define CLK_UART1 37 macro
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| D | actions,s900-cmu.h | 86 #define CLK_UART1 68 macro
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| D | pistachio-clk.h | 40 #define CLK_UART1 49 macro
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| D | exynos5250.h | 94 #define CLK_UART1 290 macro
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| D | s5pv210.h | 160 #define CLK_UART1 142 macro
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| D | exynos4.h | 151 #define CLK_UART1 313 macro
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| D | exynos5420.h | 67 #define CLK_UART1 258 macro
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| D | exynos3250.h | 221 #define CLK_UART1 215 macro
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| D | sprd,sc9860-clk.h | 86 #define CLK_UART1 3 macro
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| /linux-5.19.10/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 198 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
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| D | clk-s5pv210.c | 575 GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
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| D | clk-exynos5250.c | 574 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
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| D | clk-exynos3250.c | 664 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
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| /linux-5.19.10/drivers/clk/pistachio/ |
| D | clk-pistachio.c | 36 GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
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| /linux-5.19.10/arch/arm64/boot/dts/actions/ |
| D | s700.dtsi | 127 clocks = <&cmu CLK_UART1>;
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| D | s900.dtsi | 133 clocks = <&cmu CLK_UART1>;
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| /linux-5.19.10/arch/arm/boot/dts/ |
| D | s5pv210.dtsi | 331 clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
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| D | owl-s500.dtsi | 144 clocks = <&cmu CLK_UART1>;
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| D | exynos5410.dtsi | 347 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| /linux-5.19.10/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 91 <&ap_clk CLK_UART1>, <&ext_26m>;
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| /linux-5.19.10/drivers/clk/actions/ |
| D | owl-s500.c | 490 [CLK_UART1] = &uart1_clk.common.hw,
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| D | owl-s700.c | 529 [CLK_UART1] = &clk_uart1.common.hw,
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| D | owl-s900.c | 677 [CLK_UART1] = &uart1_clk.common.hw,
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