1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
4 *
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Kevin Hilman <khilman@baylibre.com>
7 */
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/iopoll.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/ioport.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/mmc/host.h>
19 #include <linux/mmc/mmc.h>
20 #include <linux/mmc/sdio.h>
21 #include <linux/mmc/slot-gpio.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24 #include <linux/clk-provider.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/reset.h>
27 #include <linux/interrupt.h>
28 #include <linux/bitfield.h>
29 #include <linux/pinctrl/consumer.h>
30
31 #define DRIVER_NAME "meson-gx-mmc"
32
33 #define SD_EMMC_CLOCK 0x0
34 #define CLK_DIV_MASK GENMASK(5, 0)
35 #define CLK_SRC_MASK GENMASK(7, 6)
36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
37 #define CLK_TX_PHASE_MASK GENMASK(11, 10)
38 #define CLK_RX_PHASE_MASK GENMASK(13, 12)
39 #define CLK_PHASE_0 0
40 #define CLK_PHASE_180 2
41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
43 #define CLK_V2_ALWAYS_ON BIT(24)
44
45 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
46 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
47 #define CLK_V3_ALWAYS_ON BIT(28)
48
49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
51 #define CLK_ALWAYS_ON(h) (h->data->always_on)
52
53 #define SD_EMMC_DELAY 0x4
54 #define SD_EMMC_ADJUST 0x8
55 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
56 #define ADJUST_DS_EN BIT(15)
57 #define ADJUST_ADJ_EN BIT(13)
58
59 #define SD_EMMC_DELAY1 0x4
60 #define SD_EMMC_DELAY2 0x8
61 #define SD_EMMC_V3_ADJUST 0xc
62
63 #define SD_EMMC_CALOUT 0x10
64 #define SD_EMMC_START 0x40
65 #define START_DESC_INIT BIT(0)
66 #define START_DESC_BUSY BIT(1)
67 #define START_DESC_ADDR_MASK GENMASK(31, 2)
68
69 #define SD_EMMC_CFG 0x44
70 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
71 #define CFG_BUS_WIDTH_1 0x0
72 #define CFG_BUS_WIDTH_4 0x1
73 #define CFG_BUS_WIDTH_8 0x2
74 #define CFG_DDR BIT(2)
75 #define CFG_BLK_LEN_MASK GENMASK(7, 4)
76 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
77 #define CFG_RC_CC_MASK GENMASK(15, 12)
78 #define CFG_STOP_CLOCK BIT(22)
79 #define CFG_CLK_ALWAYS_ON BIT(18)
80 #define CFG_CHK_DS BIT(20)
81 #define CFG_AUTO_CLK BIT(23)
82 #define CFG_ERR_ABORT BIT(27)
83
84 #define SD_EMMC_STATUS 0x48
85 #define STATUS_BUSY BIT(31)
86 #define STATUS_DESC_BUSY BIT(30)
87 #define STATUS_DATI GENMASK(23, 16)
88
89 #define SD_EMMC_IRQ_EN 0x4c
90 #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
91 #define IRQ_TXD_ERR BIT(8)
92 #define IRQ_DESC_ERR BIT(9)
93 #define IRQ_RESP_ERR BIT(10)
94 #define IRQ_CRC_ERR \
95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
96 #define IRQ_RESP_TIMEOUT BIT(11)
97 #define IRQ_DESC_TIMEOUT BIT(12)
98 #define IRQ_TIMEOUTS \
99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
100 #define IRQ_END_OF_CHAIN BIT(13)
101 #define IRQ_RESP_STATUS BIT(14)
102 #define IRQ_SDIO BIT(15)
103 #define IRQ_EN_MASK \
104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
105 IRQ_SDIO)
106
107 #define SD_EMMC_CMD_CFG 0x50
108 #define SD_EMMC_CMD_ARG 0x54
109 #define SD_EMMC_CMD_DAT 0x58
110 #define SD_EMMC_CMD_RSP 0x5c
111 #define SD_EMMC_CMD_RSP1 0x60
112 #define SD_EMMC_CMD_RSP2 0x64
113 #define SD_EMMC_CMD_RSP3 0x68
114
115 #define SD_EMMC_RXD 0x94
116 #define SD_EMMC_TXD 0x94
117 #define SD_EMMC_LAST_REG SD_EMMC_TXD
118
119 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536
120 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
121
122 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
123 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
124 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
125 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
126 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
127 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
128
129 #define SD_EMMC_PRE_REQ_DONE BIT(0)
130 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
131
132 #define MUX_CLK_NUM_PARENTS 2
133
134 struct meson_mmc_data {
135 unsigned int tx_delay_mask;
136 unsigned int rx_delay_mask;
137 unsigned int always_on;
138 unsigned int adjust;
139 };
140
141 struct sd_emmc_desc {
142 u32 cmd_cfg;
143 u32 cmd_arg;
144 u32 cmd_data;
145 u32 cmd_resp;
146 };
147
148 struct meson_host {
149 struct device *dev;
150 struct meson_mmc_data *data;
151 struct mmc_host *mmc;
152 struct mmc_command *cmd;
153
154 void __iomem *regs;
155 struct clk *core_clk;
156 struct clk *mux_clk;
157 struct clk *mmc_clk;
158 unsigned long req_rate;
159 bool ddr;
160
161 bool dram_access_quirk;
162
163 struct pinctrl *pinctrl;
164 struct pinctrl_state *pins_clk_gate;
165
166 unsigned int bounce_buf_size;
167 void *bounce_buf;
168 void __iomem *bounce_iomem_buf;
169 dma_addr_t bounce_dma_addr;
170 struct sd_emmc_desc *descs;
171 dma_addr_t descs_dma_addr;
172
173 int irq;
174
175 bool vqmmc_enabled;
176 bool needs_pre_post_req;
177
178 };
179
180 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
181 #define CMD_CFG_BLOCK_MODE BIT(9)
182 #define CMD_CFG_R1B BIT(10)
183 #define CMD_CFG_END_OF_CHAIN BIT(11)
184 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
185 #define CMD_CFG_NO_RESP BIT(16)
186 #define CMD_CFG_NO_CMD BIT(17)
187 #define CMD_CFG_DATA_IO BIT(18)
188 #define CMD_CFG_DATA_WR BIT(19)
189 #define CMD_CFG_RESP_NOCRC BIT(20)
190 #define CMD_CFG_RESP_128 BIT(21)
191 #define CMD_CFG_RESP_NUM BIT(22)
192 #define CMD_CFG_DATA_NUM BIT(23)
193 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
194 #define CMD_CFG_ERROR BIT(30)
195 #define CMD_CFG_OWNER BIT(31)
196
197 #define CMD_DATA_MASK GENMASK(31, 2)
198 #define CMD_DATA_BIG_ENDIAN BIT(1)
199 #define CMD_DATA_SRAM BIT(0)
200 #define CMD_RESP_MASK GENMASK(31, 1)
201 #define CMD_RESP_SRAM BIT(0)
202
meson_mmc_get_timeout_msecs(struct mmc_data * data)203 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
204 {
205 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
206
207 if (!timeout)
208 return SD_EMMC_CMD_TIMEOUT_DATA;
209
210 timeout = roundup_pow_of_two(timeout);
211
212 return min(timeout, 32768U); /* max. 2^15 ms */
213 }
214
meson_mmc_get_next_command(struct mmc_command * cmd)215 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
216 {
217 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
218 return cmd->mrq->cmd;
219 else if (mmc_op_multi(cmd->opcode) &&
220 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
221 return cmd->mrq->stop;
222 else
223 return NULL;
224 }
225
meson_mmc_get_transfer_mode(struct mmc_host * mmc,struct mmc_request * mrq)226 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
227 struct mmc_request *mrq)
228 {
229 struct meson_host *host = mmc_priv(mmc);
230 struct mmc_data *data = mrq->data;
231 struct scatterlist *sg;
232 int i;
233
234 /*
235 * When Controller DMA cannot directly access DDR memory, disable
236 * support for Chain Mode to directly use the internal SRAM using
237 * the bounce buffer mode.
238 */
239 if (host->dram_access_quirk)
240 return;
241
242 /* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */
243 if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) {
244 /*
245 * In block mode DMA descriptor format, "length" field indicates
246 * number of blocks and there is no way to pass DMA size that
247 * is not multiple of SDIO block size, making it impossible to
248 * tie more than one memory buffer with single SDIO block.
249 * Block mode sg buffer size should be aligned with SDIO block
250 * size, otherwise chain mode could not be used.
251 */
252 for_each_sg(data->sg, sg, data->sg_len, i) {
253 if (sg->length % data->blksz) {
254 dev_warn_once(mmc_dev(mmc),
255 "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n",
256 sg->length, data->blksz);
257 return;
258 }
259 }
260 }
261
262 for_each_sg(data->sg, sg, data->sg_len, i) {
263 /* check for 8 byte alignment */
264 if (sg->offset % 8) {
265 dev_warn_once(mmc_dev(mmc),
266 "unaligned sg offset %u, disabling descriptor DMA for transfer\n",
267 sg->offset);
268 return;
269 }
270 }
271
272 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
273 }
274
meson_mmc_desc_chain_mode(const struct mmc_data * data)275 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
276 {
277 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
278 }
279
meson_mmc_bounce_buf_read(const struct mmc_data * data)280 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
281 {
282 return data && data->flags & MMC_DATA_READ &&
283 !meson_mmc_desc_chain_mode(data);
284 }
285
meson_mmc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)286 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
287 {
288 struct mmc_data *data = mrq->data;
289
290 if (!data)
291 return;
292
293 meson_mmc_get_transfer_mode(mmc, mrq);
294 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
295
296 if (!meson_mmc_desc_chain_mode(data))
297 return;
298
299 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
300 mmc_get_dma_dir(data));
301 if (!data->sg_count)
302 dev_err(mmc_dev(mmc), "dma_map_sg failed");
303 }
304
meson_mmc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)305 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
306 int err)
307 {
308 struct mmc_data *data = mrq->data;
309
310 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
311 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
312 mmc_get_dma_dir(data));
313 }
314
315 /*
316 * Gating the clock on this controller is tricky. It seems the mmc clock
317 * is also used by the controller. It may crash during some operation if the
318 * clock is stopped. The safest thing to do, whenever possible, is to keep
319 * clock running at stop it at the pad using the pinmux.
320 */
meson_mmc_clk_gate(struct meson_host * host)321 static void meson_mmc_clk_gate(struct meson_host *host)
322 {
323 u32 cfg;
324
325 if (host->pins_clk_gate) {
326 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
327 } else {
328 /*
329 * If the pinmux is not provided - default to the classic and
330 * unsafe method
331 */
332 cfg = readl(host->regs + SD_EMMC_CFG);
333 cfg |= CFG_STOP_CLOCK;
334 writel(cfg, host->regs + SD_EMMC_CFG);
335 }
336 }
337
meson_mmc_clk_ungate(struct meson_host * host)338 static void meson_mmc_clk_ungate(struct meson_host *host)
339 {
340 u32 cfg;
341
342 if (host->pins_clk_gate)
343 pinctrl_select_default_state(host->dev);
344
345 /* Make sure the clock is not stopped in the controller */
346 cfg = readl(host->regs + SD_EMMC_CFG);
347 cfg &= ~CFG_STOP_CLOCK;
348 writel(cfg, host->regs + SD_EMMC_CFG);
349 }
350
meson_mmc_clk_set(struct meson_host * host,unsigned long rate,bool ddr)351 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
352 bool ddr)
353 {
354 struct mmc_host *mmc = host->mmc;
355 int ret;
356 u32 cfg;
357
358 /* Same request - bail-out */
359 if (host->ddr == ddr && host->req_rate == rate)
360 return 0;
361
362 /* stop clock */
363 meson_mmc_clk_gate(host);
364 host->req_rate = 0;
365 mmc->actual_clock = 0;
366
367 /* return with clock being stopped */
368 if (!rate)
369 return 0;
370
371 /* Stop the clock during rate change to avoid glitches */
372 cfg = readl(host->regs + SD_EMMC_CFG);
373 cfg |= CFG_STOP_CLOCK;
374 writel(cfg, host->regs + SD_EMMC_CFG);
375
376 if (ddr) {
377 /* DDR modes require higher module clock */
378 rate <<= 1;
379 cfg |= CFG_DDR;
380 } else {
381 cfg &= ~CFG_DDR;
382 }
383 writel(cfg, host->regs + SD_EMMC_CFG);
384 host->ddr = ddr;
385
386 ret = clk_set_rate(host->mmc_clk, rate);
387 if (ret) {
388 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
389 rate, ret);
390 return ret;
391 }
392
393 host->req_rate = rate;
394 mmc->actual_clock = clk_get_rate(host->mmc_clk);
395
396 /* We should report the real output frequency of the controller */
397 if (ddr) {
398 host->req_rate >>= 1;
399 mmc->actual_clock >>= 1;
400 }
401
402 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
403 if (rate != mmc->actual_clock)
404 dev_dbg(host->dev, "requested rate was %lu\n", rate);
405
406 /* (re)start clock */
407 meson_mmc_clk_ungate(host);
408
409 return 0;
410 }
411
412 /*
413 * The SD/eMMC IP block has an internal mux and divider used for
414 * generating the MMC clock. Use the clock framework to create and
415 * manage these clocks.
416 */
meson_mmc_clk_init(struct meson_host * host)417 static int meson_mmc_clk_init(struct meson_host *host)
418 {
419 struct clk_init_data init;
420 struct clk_mux *mux;
421 struct clk_divider *div;
422 char clk_name[32];
423 int i, ret = 0;
424 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
425 const char *clk_parent[1];
426 u32 clk_reg;
427
428 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
429 clk_reg = CLK_ALWAYS_ON(host);
430 clk_reg |= CLK_DIV_MASK;
431 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
432 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
433 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
434 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
435
436 /* get the mux parents */
437 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
438 struct clk *clk;
439 char name[16];
440
441 snprintf(name, sizeof(name), "clkin%d", i);
442 clk = devm_clk_get(host->dev, name);
443 if (IS_ERR(clk))
444 return dev_err_probe(host->dev, PTR_ERR(clk),
445 "Missing clock %s\n", name);
446
447 mux_parent_names[i] = __clk_get_name(clk);
448 }
449
450 /* create the mux */
451 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
452 if (!mux)
453 return -ENOMEM;
454
455 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
456 init.name = clk_name;
457 init.ops = &clk_mux_ops;
458 init.flags = 0;
459 init.parent_names = mux_parent_names;
460 init.num_parents = MUX_CLK_NUM_PARENTS;
461
462 mux->reg = host->regs + SD_EMMC_CLOCK;
463 mux->shift = __ffs(CLK_SRC_MASK);
464 mux->mask = CLK_SRC_MASK >> mux->shift;
465 mux->hw.init = &init;
466
467 host->mux_clk = devm_clk_register(host->dev, &mux->hw);
468 if (WARN_ON(IS_ERR(host->mux_clk)))
469 return PTR_ERR(host->mux_clk);
470
471 /* create the divider */
472 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
473 if (!div)
474 return -ENOMEM;
475
476 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
477 init.name = clk_name;
478 init.ops = &clk_divider_ops;
479 init.flags = CLK_SET_RATE_PARENT;
480 clk_parent[0] = __clk_get_name(host->mux_clk);
481 init.parent_names = clk_parent;
482 init.num_parents = 1;
483
484 div->reg = host->regs + SD_EMMC_CLOCK;
485 div->shift = __ffs(CLK_DIV_MASK);
486 div->width = __builtin_popcountl(CLK_DIV_MASK);
487 div->hw.init = &init;
488 div->flags = CLK_DIVIDER_ONE_BASED;
489
490 host->mmc_clk = devm_clk_register(host->dev, &div->hw);
491 if (WARN_ON(IS_ERR(host->mmc_clk)))
492 return PTR_ERR(host->mmc_clk);
493
494 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
495 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
496 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
497 if (ret)
498 return ret;
499
500 return clk_prepare_enable(host->mmc_clk);
501 }
502
meson_mmc_disable_resampling(struct meson_host * host)503 static void meson_mmc_disable_resampling(struct meson_host *host)
504 {
505 unsigned int val = readl(host->regs + host->data->adjust);
506
507 val &= ~ADJUST_ADJ_EN;
508 writel(val, host->regs + host->data->adjust);
509 }
510
meson_mmc_reset_resampling(struct meson_host * host)511 static void meson_mmc_reset_resampling(struct meson_host *host)
512 {
513 unsigned int val;
514
515 meson_mmc_disable_resampling(host);
516
517 val = readl(host->regs + host->data->adjust);
518 val &= ~ADJUST_ADJ_DELAY_MASK;
519 writel(val, host->regs + host->data->adjust);
520 }
521
meson_mmc_resampling_tuning(struct mmc_host * mmc,u32 opcode)522 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
523 {
524 struct meson_host *host = mmc_priv(mmc);
525 unsigned int val, dly, max_dly, i;
526 int ret;
527
528 /* Resampling is done using the source clock */
529 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
530 clk_get_rate(host->mmc_clk));
531
532 val = readl(host->regs + host->data->adjust);
533 val |= ADJUST_ADJ_EN;
534 writel(val, host->regs + host->data->adjust);
535
536 if (mmc_doing_retune(mmc))
537 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
538 else
539 dly = 0;
540
541 for (i = 0; i < max_dly; i++) {
542 val &= ~ADJUST_ADJ_DELAY_MASK;
543 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
544 writel(val, host->regs + host->data->adjust);
545
546 ret = mmc_send_tuning(mmc, opcode, NULL);
547 if (!ret) {
548 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
549 (dly + i) % max_dly);
550 return 0;
551 }
552 }
553
554 meson_mmc_reset_resampling(host);
555 return -EIO;
556 }
557
meson_mmc_prepare_ios_clock(struct meson_host * host,struct mmc_ios * ios)558 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
559 struct mmc_ios *ios)
560 {
561 bool ddr;
562
563 switch (ios->timing) {
564 case MMC_TIMING_MMC_DDR52:
565 case MMC_TIMING_UHS_DDR50:
566 ddr = true;
567 break;
568
569 default:
570 ddr = false;
571 break;
572 }
573
574 return meson_mmc_clk_set(host, ios->clock, ddr);
575 }
576
meson_mmc_check_resampling(struct meson_host * host,struct mmc_ios * ios)577 static void meson_mmc_check_resampling(struct meson_host *host,
578 struct mmc_ios *ios)
579 {
580 switch (ios->timing) {
581 case MMC_TIMING_LEGACY:
582 case MMC_TIMING_MMC_HS:
583 case MMC_TIMING_SD_HS:
584 case MMC_TIMING_MMC_DDR52:
585 meson_mmc_disable_resampling(host);
586 break;
587 }
588 }
589
meson_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)590 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
591 {
592 struct meson_host *host = mmc_priv(mmc);
593 u32 bus_width, val;
594 int err;
595
596 /*
597 * GPIO regulator, only controls switching between 1v8 and
598 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
599 */
600 switch (ios->power_mode) {
601 case MMC_POWER_OFF:
602 if (!IS_ERR(mmc->supply.vmmc))
603 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
604
605 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
606 regulator_disable(mmc->supply.vqmmc);
607 host->vqmmc_enabled = false;
608 }
609
610 break;
611
612 case MMC_POWER_UP:
613 if (!IS_ERR(mmc->supply.vmmc))
614 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
615
616 break;
617
618 case MMC_POWER_ON:
619 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
620 int ret = regulator_enable(mmc->supply.vqmmc);
621
622 if (ret < 0)
623 dev_err(host->dev,
624 "failed to enable vqmmc regulator\n");
625 else
626 host->vqmmc_enabled = true;
627 }
628
629 break;
630 }
631
632 /* Bus width */
633 switch (ios->bus_width) {
634 case MMC_BUS_WIDTH_1:
635 bus_width = CFG_BUS_WIDTH_1;
636 break;
637 case MMC_BUS_WIDTH_4:
638 bus_width = CFG_BUS_WIDTH_4;
639 break;
640 case MMC_BUS_WIDTH_8:
641 bus_width = CFG_BUS_WIDTH_8;
642 break;
643 default:
644 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
645 ios->bus_width);
646 bus_width = CFG_BUS_WIDTH_4;
647 }
648
649 val = readl(host->regs + SD_EMMC_CFG);
650 val &= ~CFG_BUS_WIDTH_MASK;
651 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
652 writel(val, host->regs + SD_EMMC_CFG);
653
654 meson_mmc_check_resampling(host, ios);
655 err = meson_mmc_prepare_ios_clock(host, ios);
656 if (err)
657 dev_err(host->dev, "Failed to set clock: %d\n,", err);
658
659 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
660 }
661
meson_mmc_request_done(struct mmc_host * mmc,struct mmc_request * mrq)662 static void meson_mmc_request_done(struct mmc_host *mmc,
663 struct mmc_request *mrq)
664 {
665 struct meson_host *host = mmc_priv(mmc);
666
667 host->cmd = NULL;
668 if (host->needs_pre_post_req)
669 meson_mmc_post_req(mmc, mrq, 0);
670 mmc_request_done(host->mmc, mrq);
671 }
672
meson_mmc_set_blksz(struct mmc_host * mmc,unsigned int blksz)673 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
674 {
675 struct meson_host *host = mmc_priv(mmc);
676 u32 cfg, blksz_old;
677
678 cfg = readl(host->regs + SD_EMMC_CFG);
679 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
680
681 if (!is_power_of_2(blksz))
682 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
683
684 blksz = ilog2(blksz);
685
686 /* check if block-size matches, if not update */
687 if (blksz == blksz_old)
688 return;
689
690 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
691 blksz_old, blksz);
692
693 cfg &= ~CFG_BLK_LEN_MASK;
694 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
695 writel(cfg, host->regs + SD_EMMC_CFG);
696 }
697
meson_mmc_set_response_bits(struct mmc_command * cmd,u32 * cmd_cfg)698 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
699 {
700 if (cmd->flags & MMC_RSP_PRESENT) {
701 if (cmd->flags & MMC_RSP_136)
702 *cmd_cfg |= CMD_CFG_RESP_128;
703 *cmd_cfg |= CMD_CFG_RESP_NUM;
704
705 if (!(cmd->flags & MMC_RSP_CRC))
706 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
707
708 if (cmd->flags & MMC_RSP_BUSY)
709 *cmd_cfg |= CMD_CFG_R1B;
710 } else {
711 *cmd_cfg |= CMD_CFG_NO_RESP;
712 }
713 }
714
meson_mmc_desc_chain_transfer(struct mmc_host * mmc,u32 cmd_cfg)715 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
716 {
717 struct meson_host *host = mmc_priv(mmc);
718 struct sd_emmc_desc *desc = host->descs;
719 struct mmc_data *data = host->cmd->data;
720 struct scatterlist *sg;
721 u32 start;
722 int i;
723
724 if (data->flags & MMC_DATA_WRITE)
725 cmd_cfg |= CMD_CFG_DATA_WR;
726
727 if (data->blocks > 1) {
728 cmd_cfg |= CMD_CFG_BLOCK_MODE;
729 meson_mmc_set_blksz(mmc, data->blksz);
730 }
731
732 for_each_sg(data->sg, sg, data->sg_count, i) {
733 unsigned int len = sg_dma_len(sg);
734
735 if (data->blocks > 1)
736 len /= data->blksz;
737
738 desc[i].cmd_cfg = cmd_cfg;
739 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
740 if (i > 0)
741 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
742 desc[i].cmd_arg = host->cmd->arg;
743 desc[i].cmd_resp = 0;
744 desc[i].cmd_data = sg_dma_address(sg);
745 }
746 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
747
748 dma_wmb(); /* ensure descriptor is written before kicked */
749 start = host->descs_dma_addr | START_DESC_BUSY;
750 writel(start, host->regs + SD_EMMC_START);
751 }
752
753 /* local sg copy for dram_access_quirk */
meson_mmc_copy_buffer(struct meson_host * host,struct mmc_data * data,size_t buflen,bool to_buffer)754 static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
755 size_t buflen, bool to_buffer)
756 {
757 unsigned int sg_flags = SG_MITER_ATOMIC;
758 struct scatterlist *sgl = data->sg;
759 unsigned int nents = data->sg_len;
760 struct sg_mapping_iter miter;
761 unsigned int offset = 0;
762
763 if (to_buffer)
764 sg_flags |= SG_MITER_FROM_SG;
765 else
766 sg_flags |= SG_MITER_TO_SG;
767
768 sg_miter_start(&miter, sgl, nents, sg_flags);
769
770 while ((offset < buflen) && sg_miter_next(&miter)) {
771 unsigned int buf_offset = 0;
772 unsigned int len, left;
773 u32 *buf = miter.addr;
774
775 len = min(miter.length, buflen - offset);
776 left = len;
777
778 if (to_buffer) {
779 do {
780 writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
781
782 buf_offset += 4;
783 left -= 4;
784 } while (left);
785 } else {
786 do {
787 *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
788
789 buf_offset += 4;
790 left -= 4;
791 } while (left);
792 }
793
794 offset += len;
795 }
796
797 sg_miter_stop(&miter);
798 }
799
meson_mmc_start_cmd(struct mmc_host * mmc,struct mmc_command * cmd)800 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
801 {
802 struct meson_host *host = mmc_priv(mmc);
803 struct mmc_data *data = cmd->data;
804 u32 cmd_cfg = 0, cmd_data = 0;
805 unsigned int xfer_bytes = 0;
806
807 /* Setup descriptors */
808 dma_rmb();
809
810 host->cmd = cmd;
811
812 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
813 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
814 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */
815
816 meson_mmc_set_response_bits(cmd, &cmd_cfg);
817
818 /* data? */
819 if (data) {
820 data->bytes_xfered = 0;
821 cmd_cfg |= CMD_CFG_DATA_IO;
822 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
823 ilog2(meson_mmc_get_timeout_msecs(data)));
824
825 if (meson_mmc_desc_chain_mode(data)) {
826 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
827 return;
828 }
829
830 if (data->blocks > 1) {
831 cmd_cfg |= CMD_CFG_BLOCK_MODE;
832 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
833 data->blocks);
834 meson_mmc_set_blksz(mmc, data->blksz);
835 } else {
836 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
837 }
838
839 xfer_bytes = data->blksz * data->blocks;
840 if (data->flags & MMC_DATA_WRITE) {
841 cmd_cfg |= CMD_CFG_DATA_WR;
842 WARN_ON(xfer_bytes > host->bounce_buf_size);
843 if (host->dram_access_quirk)
844 meson_mmc_copy_buffer(host, data, xfer_bytes, true);
845 else
846 sg_copy_to_buffer(data->sg, data->sg_len,
847 host->bounce_buf, xfer_bytes);
848 dma_wmb();
849 }
850
851 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
852 } else {
853 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
854 ilog2(SD_EMMC_CMD_TIMEOUT));
855 }
856
857 /* Last descriptor */
858 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
859 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
860 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
861 writel(0, host->regs + SD_EMMC_CMD_RSP);
862 wmb(); /* ensure descriptor is written before kicked */
863 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
864 }
865
meson_mmc_validate_dram_access(struct mmc_host * mmc,struct mmc_data * data)866 static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data)
867 {
868 struct scatterlist *sg;
869 int i;
870
871 /* Reject request if any element offset or size is not 32bit aligned */
872 for_each_sg(data->sg, sg, data->sg_len, i) {
873 if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
874 !IS_ALIGNED(sg->length, sizeof(u32))) {
875 dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",
876 data->sg->offset, data->sg->length);
877 return -EINVAL;
878 }
879 }
880
881 return 0;
882 }
883
meson_mmc_request(struct mmc_host * mmc,struct mmc_request * mrq)884 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
885 {
886 struct meson_host *host = mmc_priv(mmc);
887 host->needs_pre_post_req = mrq->data &&
888 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
889
890 /*
891 * The memory at the end of the controller used as bounce buffer for
892 * the dram_access_quirk only accepts 32bit read/write access,
893 * check the aligment and length of the data before starting the request.
894 */
895 if (host->dram_access_quirk && mrq->data) {
896 mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
897 if (mrq->cmd->error) {
898 mmc_request_done(mmc, mrq);
899 return;
900 }
901 }
902
903 if (host->needs_pre_post_req) {
904 meson_mmc_get_transfer_mode(mmc, mrq);
905 if (!meson_mmc_desc_chain_mode(mrq->data))
906 host->needs_pre_post_req = false;
907 }
908
909 if (host->needs_pre_post_req)
910 meson_mmc_pre_req(mmc, mrq);
911
912 /* Stop execution */
913 writel(0, host->regs + SD_EMMC_START);
914
915 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
916 }
917
meson_mmc_read_resp(struct mmc_host * mmc,struct mmc_command * cmd)918 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
919 {
920 struct meson_host *host = mmc_priv(mmc);
921
922 if (cmd->flags & MMC_RSP_136) {
923 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
924 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
925 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
926 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
927 } else if (cmd->flags & MMC_RSP_PRESENT) {
928 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
929 }
930 }
931
meson_mmc_irq(int irq,void * dev_id)932 static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
933 {
934 struct meson_host *host = dev_id;
935 struct mmc_command *cmd;
936 struct mmc_data *data;
937 u32 irq_en, status, raw_status;
938 irqreturn_t ret = IRQ_NONE;
939
940 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
941 raw_status = readl(host->regs + SD_EMMC_STATUS);
942 status = raw_status & irq_en;
943
944 if (!status) {
945 dev_dbg(host->dev,
946 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
947 irq_en, raw_status);
948 return IRQ_NONE;
949 }
950
951 if (WARN_ON(!host) || WARN_ON(!host->cmd))
952 return IRQ_NONE;
953
954 /* ack all raised interrupts */
955 writel(status, host->regs + SD_EMMC_STATUS);
956
957 cmd = host->cmd;
958 data = cmd->data;
959 cmd->error = 0;
960 if (status & IRQ_CRC_ERR) {
961 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
962 cmd->error = -EILSEQ;
963 ret = IRQ_WAKE_THREAD;
964 goto out;
965 }
966
967 if (status & IRQ_TIMEOUTS) {
968 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
969 cmd->error = -ETIMEDOUT;
970 ret = IRQ_WAKE_THREAD;
971 goto out;
972 }
973
974 meson_mmc_read_resp(host->mmc, cmd);
975
976 if (status & IRQ_SDIO) {
977 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
978 ret = IRQ_HANDLED;
979 }
980
981 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
982 if (data && !cmd->error)
983 data->bytes_xfered = data->blksz * data->blocks;
984 if (meson_mmc_bounce_buf_read(data) ||
985 meson_mmc_get_next_command(cmd))
986 ret = IRQ_WAKE_THREAD;
987 else
988 ret = IRQ_HANDLED;
989 }
990
991 out:
992 if (cmd->error) {
993 /* Stop desc in case of errors */
994 u32 start = readl(host->regs + SD_EMMC_START);
995
996 start &= ~START_DESC_BUSY;
997 writel(start, host->regs + SD_EMMC_START);
998 }
999
1000 if (ret == IRQ_HANDLED)
1001 meson_mmc_request_done(host->mmc, cmd->mrq);
1002
1003 return ret;
1004 }
1005
meson_mmc_wait_desc_stop(struct meson_host * host)1006 static int meson_mmc_wait_desc_stop(struct meson_host *host)
1007 {
1008 u32 status;
1009
1010 /*
1011 * It may sometimes take a while for it to actually halt. Here, we
1012 * are giving it 5ms to comply
1013 *
1014 * If we don't confirm the descriptor is stopped, it might raise new
1015 * IRQs after we have called mmc_request_done() which is bad.
1016 */
1017
1018 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
1019 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
1020 100, 5000);
1021 }
1022
meson_mmc_irq_thread(int irq,void * dev_id)1023 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1024 {
1025 struct meson_host *host = dev_id;
1026 struct mmc_command *next_cmd, *cmd = host->cmd;
1027 struct mmc_data *data;
1028 unsigned int xfer_bytes;
1029
1030 if (WARN_ON(!cmd))
1031 return IRQ_NONE;
1032
1033 if (cmd->error) {
1034 meson_mmc_wait_desc_stop(host);
1035 meson_mmc_request_done(host->mmc, cmd->mrq);
1036
1037 return IRQ_HANDLED;
1038 }
1039
1040 data = cmd->data;
1041 if (meson_mmc_bounce_buf_read(data)) {
1042 xfer_bytes = data->blksz * data->blocks;
1043 WARN_ON(xfer_bytes > host->bounce_buf_size);
1044 if (host->dram_access_quirk)
1045 meson_mmc_copy_buffer(host, data, xfer_bytes, false);
1046 else
1047 sg_copy_from_buffer(data->sg, data->sg_len,
1048 host->bounce_buf, xfer_bytes);
1049 }
1050
1051 next_cmd = meson_mmc_get_next_command(cmd);
1052 if (next_cmd)
1053 meson_mmc_start_cmd(host->mmc, next_cmd);
1054 else
1055 meson_mmc_request_done(host->mmc, cmd->mrq);
1056
1057 return IRQ_HANDLED;
1058 }
1059
1060 /*
1061 * NOTE: we only need this until the GPIO/pinctrl driver can handle
1062 * interrupts. For now, the MMC core will use this for polling.
1063 */
meson_mmc_get_cd(struct mmc_host * mmc)1064 static int meson_mmc_get_cd(struct mmc_host *mmc)
1065 {
1066 int status = mmc_gpio_get_cd(mmc);
1067
1068 if (status == -ENOSYS)
1069 return 1; /* assume present */
1070
1071 return status;
1072 }
1073
meson_mmc_cfg_init(struct meson_host * host)1074 static void meson_mmc_cfg_init(struct meson_host *host)
1075 {
1076 u32 cfg = 0;
1077
1078 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1079 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1080 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1081 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1082
1083 /* abort chain on R/W errors */
1084 cfg |= CFG_ERR_ABORT;
1085
1086 writel(cfg, host->regs + SD_EMMC_CFG);
1087 }
1088
meson_mmc_card_busy(struct mmc_host * mmc)1089 static int meson_mmc_card_busy(struct mmc_host *mmc)
1090 {
1091 struct meson_host *host = mmc_priv(mmc);
1092 u32 regval;
1093
1094 regval = readl(host->regs + SD_EMMC_STATUS);
1095
1096 /* We are only interrested in lines 0 to 3, so mask the other ones */
1097 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1098 }
1099
meson_mmc_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)1100 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1101 {
1102 int ret;
1103
1104 /* vqmmc regulator is available */
1105 if (!IS_ERR(mmc->supply.vqmmc)) {
1106 /*
1107 * The usual amlogic setup uses a GPIO to switch from one
1108 * regulator to the other. While the voltage ramp up is
1109 * pretty fast, care must be taken when switching from 3.3v
1110 * to 1.8v. Please make sure the regulator framework is aware
1111 * of your own regulator constraints
1112 */
1113 ret = mmc_regulator_set_vqmmc(mmc, ios);
1114 return ret < 0 ? ret : 0;
1115 }
1116
1117 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1118 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1119 return 0;
1120
1121 return -EINVAL;
1122 }
1123
1124 static const struct mmc_host_ops meson_mmc_ops = {
1125 .request = meson_mmc_request,
1126 .set_ios = meson_mmc_set_ios,
1127 .get_cd = meson_mmc_get_cd,
1128 .pre_req = meson_mmc_pre_req,
1129 .post_req = meson_mmc_post_req,
1130 .execute_tuning = meson_mmc_resampling_tuning,
1131 .card_busy = meson_mmc_card_busy,
1132 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1133 };
1134
meson_mmc_probe(struct platform_device * pdev)1135 static int meson_mmc_probe(struct platform_device *pdev)
1136 {
1137 struct resource *res;
1138 struct meson_host *host;
1139 struct mmc_host *mmc;
1140 int ret;
1141
1142 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1143 if (!mmc)
1144 return -ENOMEM;
1145 host = mmc_priv(mmc);
1146 host->mmc = mmc;
1147 host->dev = &pdev->dev;
1148 dev_set_drvdata(&pdev->dev, host);
1149
1150 /* The G12A SDIO Controller needs an SRAM bounce buffer */
1151 host->dram_access_quirk = device_property_read_bool(&pdev->dev,
1152 "amlogic,dram-access-quirk");
1153
1154 /* Get regulators and the supported OCR mask */
1155 host->vqmmc_enabled = false;
1156 ret = mmc_regulator_get_supply(mmc);
1157 if (ret)
1158 goto free_host;
1159
1160 ret = mmc_of_parse(mmc);
1161 if (ret) {
1162 if (ret != -EPROBE_DEFER)
1163 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1164 goto free_host;
1165 }
1166
1167 host->data = (struct meson_mmc_data *)
1168 of_device_get_match_data(&pdev->dev);
1169 if (!host->data) {
1170 ret = -EINVAL;
1171 goto free_host;
1172 }
1173
1174 ret = device_reset_optional(&pdev->dev);
1175 if (ret) {
1176 dev_err_probe(&pdev->dev, ret, "device reset failed\n");
1177 goto free_host;
1178 }
1179
1180 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1181 host->regs = devm_ioremap_resource(&pdev->dev, res);
1182 if (IS_ERR(host->regs)) {
1183 ret = PTR_ERR(host->regs);
1184 goto free_host;
1185 }
1186
1187 host->irq = platform_get_irq(pdev, 0);
1188 if (host->irq <= 0) {
1189 ret = -EINVAL;
1190 goto free_host;
1191 }
1192
1193 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1194 if (IS_ERR(host->pinctrl)) {
1195 ret = PTR_ERR(host->pinctrl);
1196 goto free_host;
1197 }
1198
1199 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1200 "clk-gate");
1201 if (IS_ERR(host->pins_clk_gate)) {
1202 dev_warn(&pdev->dev,
1203 "can't get clk-gate pinctrl, using clk_stop bit\n");
1204 host->pins_clk_gate = NULL;
1205 }
1206
1207 host->core_clk = devm_clk_get(&pdev->dev, "core");
1208 if (IS_ERR(host->core_clk)) {
1209 ret = PTR_ERR(host->core_clk);
1210 goto free_host;
1211 }
1212
1213 ret = clk_prepare_enable(host->core_clk);
1214 if (ret)
1215 goto free_host;
1216
1217 ret = meson_mmc_clk_init(host);
1218 if (ret)
1219 goto err_core_clk;
1220
1221 /* set config to sane default */
1222 meson_mmc_cfg_init(host);
1223
1224 /* Stop execution */
1225 writel(0, host->regs + SD_EMMC_START);
1226
1227 /* clear, ack and enable interrupts */
1228 writel(0, host->regs + SD_EMMC_IRQ_EN);
1229 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1230 host->regs + SD_EMMC_STATUS);
1231 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1232 host->regs + SD_EMMC_IRQ_EN);
1233
1234 ret = request_threaded_irq(host->irq, meson_mmc_irq,
1235 meson_mmc_irq_thread, IRQF_ONESHOT,
1236 dev_name(&pdev->dev), host);
1237 if (ret)
1238 goto err_init_clk;
1239
1240 mmc->caps |= MMC_CAP_CMD23;
1241 if (host->dram_access_quirk) {
1242 /* Limit segments to 1 due to low available sram memory */
1243 mmc->max_segs = 1;
1244 /* Limit to the available sram memory */
1245 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
1246 mmc->max_blk_size;
1247 } else {
1248 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1249 mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
1250 sizeof(struct sd_emmc_desc);
1251 }
1252 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1253 mmc->max_seg_size = mmc->max_req_size;
1254
1255 /*
1256 * At the moment, we don't know how to reliably enable HS400.
1257 * From the different datasheets, it is not even clear if this mode
1258 * is officially supported by any of the SoCs
1259 */
1260 mmc->caps2 &= ~MMC_CAP2_HS400;
1261
1262 if (host->dram_access_quirk) {
1263 /*
1264 * The MMC Controller embeds 1,5KiB of internal SRAM
1265 * that can be used to be used as bounce buffer.
1266 * In the case of the G12A SDIO controller, use these
1267 * instead of the DDR memory
1268 */
1269 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
1270 host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
1271 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
1272 } else {
1273 /* data bounce buffer */
1274 host->bounce_buf_size = mmc->max_req_size;
1275 host->bounce_buf =
1276 dmam_alloc_coherent(host->dev, host->bounce_buf_size,
1277 &host->bounce_dma_addr, GFP_KERNEL);
1278 if (host->bounce_buf == NULL) {
1279 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1280 ret = -ENOMEM;
1281 goto err_free_irq;
1282 }
1283 }
1284
1285 host->descs = dmam_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1286 &host->descs_dma_addr, GFP_KERNEL);
1287 if (!host->descs) {
1288 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1289 ret = -ENOMEM;
1290 goto err_free_irq;
1291 }
1292
1293 mmc->ops = &meson_mmc_ops;
1294 mmc_add_host(mmc);
1295
1296 return 0;
1297
1298 err_free_irq:
1299 free_irq(host->irq, host);
1300 err_init_clk:
1301 clk_disable_unprepare(host->mmc_clk);
1302 err_core_clk:
1303 clk_disable_unprepare(host->core_clk);
1304 free_host:
1305 mmc_free_host(mmc);
1306 return ret;
1307 }
1308
meson_mmc_remove(struct platform_device * pdev)1309 static int meson_mmc_remove(struct platform_device *pdev)
1310 {
1311 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1312
1313 mmc_remove_host(host->mmc);
1314
1315 /* disable interrupts */
1316 writel(0, host->regs + SD_EMMC_IRQ_EN);
1317 free_irq(host->irq, host);
1318
1319 clk_disable_unprepare(host->mmc_clk);
1320 clk_disable_unprepare(host->core_clk);
1321
1322 mmc_free_host(host->mmc);
1323 return 0;
1324 }
1325
1326 static const struct meson_mmc_data meson_gx_data = {
1327 .tx_delay_mask = CLK_V2_TX_DELAY_MASK,
1328 .rx_delay_mask = CLK_V2_RX_DELAY_MASK,
1329 .always_on = CLK_V2_ALWAYS_ON,
1330 .adjust = SD_EMMC_ADJUST,
1331 };
1332
1333 static const struct meson_mmc_data meson_axg_data = {
1334 .tx_delay_mask = CLK_V3_TX_DELAY_MASK,
1335 .rx_delay_mask = CLK_V3_RX_DELAY_MASK,
1336 .always_on = CLK_V3_ALWAYS_ON,
1337 .adjust = SD_EMMC_V3_ADJUST,
1338 };
1339
1340 static const struct of_device_id meson_mmc_of_match[] = {
1341 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
1342 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
1343 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
1344 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
1345 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
1346 {}
1347 };
1348 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1349
1350 static struct platform_driver meson_mmc_driver = {
1351 .probe = meson_mmc_probe,
1352 .remove = meson_mmc_remove,
1353 .driver = {
1354 .name = DRIVER_NAME,
1355 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1356 .of_match_table = meson_mmc_of_match,
1357 },
1358 };
1359
1360 module_platform_driver(meson_mmc_driver);
1361
1362 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1363 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1364 MODULE_LICENSE("GPL v2");
1365