Home
last modified time | relevance | path

Searched refs:CLK_TOP_SENINF_SEL (Results 1 – 4 of 4) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dmt6765-clk.h157 #define CLK_TOP_SENINF_SEL 122 macro
Dmt8192-clk.h49 #define CLK_TOP_SENINF_SEL 37 macro
/linux-5.19.10/drivers/clk/mediatek/
Dclk-mt6765.c452 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents,
Dclk-mt8192.c795 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",