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Searched refs:CLK_TOP_MUX_UART (Results 1 – 4 of 4) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dmt6797-clk.h22 #define CLK_TOP_MUX_UART 12 macro
Dmt8183-clk.h41 #define CLK_TOP_MUX_UART 5 macro
/linux-5.19.10/drivers/clk/mediatek/
Dclk-mt6797.c340 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
Dclk-mt8183.c571 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",