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Searched refs:CLK_TOP_MSDC50_0_HCLK_SEL (Results 1 – 4 of 4) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dmt6765-clk.h143 #define CLK_TOP_MSDC50_0_HCLK_SEL 108 macro
Dmt2712-clk.h142 #define CLK_TOP_MSDC50_0_HCLK_SEL 111 macro
/linux-5.19.10/drivers/clk/mediatek/
Dclk-mt2712.c766 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
Dclk-mt6765.c407 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",