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Searched refs:CLK_TOP_CAMTG_SEL (Results 1 – 12 of 12) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dmt8135-clk.h90 #define CLK_TOP_CAMTG_SEL 79 macro
Dmt6765-clk.h137 #define CLK_TOP_CAMTG_SEL 102 macro
Dmt8173-clk.h100 #define CLK_TOP_CAMTG_SEL 90 macro
Dmt2712-clk.h137 #define CLK_TOP_CAMTG_SEL 106 macro
Dmt2701-clk.h91 #define CLK_TOP_CAMTG_SEL 80 macro
Dmt8192-clk.h27 #define CLK_TOP_CAMTG_SEL 15 macro
/linux-5.19.10/drivers/clk/mediatek/
Dclk-mt8135.c377 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
Dclk-mt2701.c504 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
Dclk-mt2712.c755 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
Dclk-mt6765.c387 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
Dclk-mt8173.c553 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
Dclk-mt8192.c745 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",