Searched refs:CLK_TOP_AUD_ENGEN1_SEL (Results 1 – 8 of 8) sorted by relevance
| /linux-5.19.10/include/dt-bindings/clock/ |
| D | mt8516-clk.h | 178 #define CLK_TOP_AUD_ENGEN1_SEL 146 macro
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| D | mt6765-clk.h | 149 #define CLK_TOP_AUD_ENGEN1_SEL 114 macro
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| D | mt8192-clk.h | 55 #define CLK_TOP_AUD_ENGEN1_SEL 43 macro
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| /linux-5.19.10/drivers/clk/mediatek/ |
| D | clk-mt8516.c | 398 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
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| D | clk-mt8167.c | 588 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
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| D | clk-mt6765.c | 426 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
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| D | clk-mt8192.c | 809 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
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| /linux-5.19.10/arch/arm64/boot/dts/mediatek/ |
| D | mt8192.dtsi | 777 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
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