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Searched refs:CLK_TOP_APLL_DIV_PDN2 (Results 1 – 2 of 2) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dmt2712-clk.h211 #define CLK_TOP_APLL_DIV_PDN2 180 macro
/linux-5.19.10/drivers/clk/mediatek/
Dclk-mt2712.c983 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),