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Searched refs:CLK_TOP_APLL_DIV4 (Results 1 – 2 of 2) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dmt2712-clk.h205 #define CLK_TOP_APLL_DIV4 174 macro
/linux-5.19.10/drivers/clk/mediatek/
Dclk-mt2712.c943 DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),