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Searched refs:CLK_SYSREG (Results 1 – 8 of 8) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dexynos5250.h123 #define CLK_SYSREG 319 macro
Dexynos4.h180 #define CLK_SYSREG 342 macro
Dexynos5420.h95 #define CLK_SYSREG 302 macro
Dexynos3250.h164 #define CLK_SYSREG 158 macro
/linux-5.19.10/drivers/clk/samsung/
Dclk-exynos4.c931 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
973 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
Dclk-exynos5250.c604 GATE(CLK_SYSREG, "sysreg", "div_aclk66",
Dclk-exynos3250.c499 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
Dclk-exynos5420.c1110 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",