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Searched refs:CLK_SSS (Results 1 – 14 of 14) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dexynos5410.h62 #define CLK_SSS 471 macro
Dexynos5250.h152 #define CLK_SSS 348 macro
Dexynos4.h93 #define CLK_SSS 255 macro
Dexynos5420.h168 #define CLK_SSS 471 macro
/linux-5.19.10/Documentation/devicetree/bindings/rng/
Dsamsung,exynos4-rng.yaml43 clocks = <&clock CLK_SSS>;
Dsamsung,exynos5250-trng.yaml42 clocks = <&clock CLK_SSS>;
/linux-5.19.10/arch/arm/boot/dts/
Dexynos5410.dtsi324 clocks = <&clock CLK_SSS>;
368 clocks = <&clock CLK_SSS>;
382 clocks = <&clock CLK_SSS>;
Dexynos5250.dtsi1176 clocks = <&clock CLK_SSS>;
1221 clocks = <&clock CLK_SSS>;
1226 clocks = <&clock CLK_SSS>;
Dexynos5420.dtsi1299 clocks = <&clock CLK_SSS>;
1344 clocks = <&clock CLK_SSS>;
1349 clocks = <&clock CLK_SSS>;
Dexynos4.dtsi995 clocks = <&clock CLK_SSS>;
1002 clocks = <&clock CLK_SSS>;
/linux-5.19.10/drivers/clk/samsung/
Dclk-exynos5410.c166 GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
Dclk-exynos5250.c445 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
Dclk-exynos4.c894 GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
Dclk-exynos5420.c930 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),