Searched refs:CLK_PDMA1 (Results 1 – 21 of 21) sorted by relevance
| /linux-5.19.10/include/dt-bindings/clock/ |
| D | exynos5410.h | 58 #define CLK_PDMA1 363 macro
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| D | exynos5250.h | 80 #define CLK_PDMA1 276 macro
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| D | s5pv210.h | 114 #define CLK_PDMA1 96 macro
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| D | exynos4.h | 131 #define CLK_PDMA1 293 macro
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| D | exynos5420.h | 123 #define CLK_PDMA1 363 macro
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| D | exynos3250.h | 206 #define CLK_PDMA1 200 macro
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| D | exynos5433.h | 571 #define CLK_PDMA1 64 macro
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| /linux-5.19.10/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 182 GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0),
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| D | clk-s5pv210.c | 632 GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
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| D | clk-exynos5250.c | 557 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
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| D | clk-exynos3250.c | 646 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
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| D | clk-exynos4.c | 837 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
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| D | clk-exynos5420.c | 1036 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
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| D | clk-exynos5433.c | 2328 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
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| /linux-5.19.10/arch/arm/boot/dts/ |
| D | exynos5410.dtsi | 205 clocks = <&clock CLK_PDMA1>;
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| D | s5pv210.dtsi | 135 clocks = <&clocks CLK_PDMA1>;
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| D | exynos3250.dtsi | 438 clocks = <&cmu CLK_PDMA1>;
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| D | exynos4.dtsi | 685 clocks = <&clock CLK_PDMA1>;
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| D | exynos5250.dtsi | 709 clocks = <&clock CLK_PDMA1>;
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| D | exynos5420.dtsi | 456 clocks = <&clock CLK_PDMA1>;
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| /linux-5.19.10/arch/arm64/boot/dts/exynos/ |
| D | exynos5433.dtsi | 1875 clocks = <&cmu_fsys CLK_PDMA1>;
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