Searched refs:CLK_MCT (Results 1 – 17 of 17) sorted by relevance
| /linux-5.19.10/Documentation/devicetree/bindings/timer/ |
| D | samsung,exynos4210-mct.yaml | 139 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
159 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
180 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
200 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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| /linux-5.19.10/include/dt-bindings/clock/ |
| D | exynos5410.h | 50 #define CLK_MCT 315 macro
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| D | exynos5250.h | 139 #define CLK_MCT 335 macro
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| D | exynos4.h | 182 #define CLK_MCT 344 macro
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| D | exynos5420.h | 108 #define CLK_MCT 315 macro
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| D | exynos3250.h | 153 #define CLK_MCT 147 macro
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| /linux-5.19.10/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 167 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
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| D | clk-exynos4.c | 945 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
985 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
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| D | clk-exynos5250.c | 625 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
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| D | clk-exynos3250.c | 478 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
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| D | clk-exynos5420.c | 1123 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
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| /linux-5.19.10/arch/arm/boot/dts/ |
| D | exynos5410.dtsi | 319 clocks = <&fin_pll>, <&clock CLK_MCT>;
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| D | exynos4210.dtsi | 125 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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| D | exynos4412.dtsi | 268 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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| D | exynos3250.dtsi | 283 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
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| D | exynos5250.dtsi | 251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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| D | exynos5420.dtsi | 1294 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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