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Searched refs:CLK_GOUT_WDT0_PCLK (Results 1 – 5 of 5) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dexynos7885.h111 #define CLK_GOUT_WDT0_PCLK 42 macro
Dexynos850.h157 #define CLK_GOUT_WDT0_PCLK 33 macro
/linux-5.19.10/drivers/clk/samsung/
Dclk-exynos7885.c472 GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
Dclk-exynos850.c809 GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
/linux-5.19.10/arch/arm64/boot/dts/exynos/
Dexynos850.dtsi218 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;