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Searched refs:CLK_DIV_MPLL_PRE (Results 1 – 4 of 4) sorted by relevance

/linux-5.19.10/arch/arm/boot/dts/
Dexynos3250-artik5-eval.dts47 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */
Dexynos3250.dtsi313 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
/linux-5.19.10/include/dt-bindings/clock/
Dexynos3250.h87 #define CLK_DIV_MPLL_PRE 68 macro
/linux-5.19.10/drivers/clk/samsung/
Dclk-exynos3250.c344 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),