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Searched refs:CLKID_VCLK_DIV12 (Results 1 – 8 of 8) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Daxg-clkc.h91 #define CLKID_VCLK_DIV12 126 macro
Dg12a-clkc.h117 #define CLKID_VCLK_DIV12 152 macro
Dgxbb-clkc.h138 #define CLKID_VCLK_DIV12 189 macro
/linux-5.19.10/drivers/clk/meson/
Dmeson8b.h134 #define CLKID_VCLK_DIV12 148 macro
Dmeson8b.c2922 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
3130 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
3349 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
Dgxbb.c2917 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
3128 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
Dg12a.c4402 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4631 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4895 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
Daxg.c2020 [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,