Searched refs:BIT_ULL (Results 1 – 25 of 386) sorted by relevance
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132 BIT_ULL(HW_ISSUE_9435))135 BIT_ULL(HW_ISSUE_6367) | \136 BIT_ULL(HW_ISSUE_6787) | \137 BIT_ULL(HW_ISSUE_8408) | \138 BIT_ULL(HW_ISSUE_9510) | \139 BIT_ULL(HW_ISSUE_10649) | \140 BIT_ULL(HW_ISSUE_10676) | \141 BIT_ULL(HW_ISSUE_10883) | \142 BIT_ULL(HW_ISSUE_11020) | \143 BIT_ULL(HW_ISSUE_11035) | \[all …]
28 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \29 BIT_ULL(HW_FEATURE_V4))36 BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \37 BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \38 BIT_ULL(HW_FEATURE_XAFFINITY) | \39 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT))50 BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \51 BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \52 BIT_ULL(HW_FEATURE_XAFFINITY) | \53 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \[all …]
361 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */362 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */363 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */364 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */365 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */366 #define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */367 #define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */368 #define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */369 #define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */370 #define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */[all …]
120 #define MIO_EMM_DMA_FIFO_CFG_CLR BIT_ULL(16)124 #define MIO_EMM_DMA_FIFO_CMD_RW BIT_ULL(62)125 #define MIO_EMM_DMA_FIFO_CMD_INTDIS BIT_ULL(60)126 #define MIO_EMM_DMA_FIFO_CMD_SWAP32 BIT_ULL(59)127 #define MIO_EMM_DMA_FIFO_CMD_SWAP16 BIT_ULL(58)128 #define MIO_EMM_DMA_FIFO_CMD_SWAP8 BIT_ULL(57)129 #define MIO_EMM_DMA_FIFO_CMD_ENDIAN BIT_ULL(56)132 #define MIO_EMM_CMD_SKIP_BUSY BIT_ULL(62)134 #define MIO_EMM_CMD_VAL BIT_ULL(59)135 #define MIO_EMM_CMD_DBUF BIT_ULL(55)[all …]
36 #define CMR_PKT_TX_EN BIT_ULL(13)37 #define CMR_PKT_RX_EN BIT_ULL(14)38 #define CMR_EN BIT_ULL(15)40 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)57 #define RX_DMACX_CAM_EN BIT_ULL(48)87 #define SPU_CTL_LOW_POWER BIT_ULL(11)88 #define SPU_CTL_LOOPBACK BIT_ULL(14)89 #define SPU_CTL_RESET BIT_ULL(15)91 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)93 #define SPU_STATUS2_RCVFLT BIT_ULL(10)[all …]
13 #define CAP_FL5LP_MASK BIT_ULL(60)14 #define CAP_PI_MASK BIT_ULL(59)15 #define CAP_FL1GP_MASK BIT_ULL(56)16 #define CAP_RD_MASK BIT_ULL(55)17 #define CAP_WD_MASK BIT_ULL(54)20 #define CAP_PSI_MASK BIT_ULL(39)23 #define CAP_ZLR_MASK BIT_ULL(22)26 #define CAP_CM_MASK BIT_ULL(7)27 #define CAP_PHMR_MASK BIT_ULL(6)28 #define CAP_PLMR_MASK BIT_ULL(5)[all …]
381 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)384 #define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)385 #define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)387 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)388 #define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)389 #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)390 #define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)394 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)397 #define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)398 #define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)[all …]
17 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)18 #define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57)22 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)23 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)24 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)39 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45)44 #define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)45 #define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5)46 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)[all …]
101 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)102 #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)103 #define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)104 #define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)105 #define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)106 #define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)107 #define LOONGARCH_CPU_COMPLEX BIT_ULL(CPU_FEATURE_COMPLEX)108 #define LOONGARCH_CPU_CRYPTO BIT_ULL(CPU_FEATURE_CRYPTO)109 #define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)110 #define LOONGARCH_CPU_LBT_X86 BIT_ULL(CPU_FEATURE_LBT_X86)[all …]
16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)18 #define KOMEDA_EVENT_URUN BIT_ULL(2)19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)20 #define KOMEDA_EVENT_OVR BIT_ULL(4)21 #define KOMEDA_EVENT_EOW BIT_ULL(5)22 #define KOMEDA_EVENT_MODE BIT_ULL(6)23 #define KOMEDA_EVENT_FULL BIT_ULL(7)24 #define KOMEDA_EVENT_EMPTY BIT_ULL(8)26 #define KOMEDA_ERR_TETO BIT_ULL(14)[all …]
13 #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */14 #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */15 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */19 #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */20 #define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */21 #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */24 #define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */25 #define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */26 #define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */27 #define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */[all …]
14 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \15 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))17 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \18 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))20 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \21 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))23 (BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \24 BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))26 (BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \27 BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))[all …]
11 #define VALID_LAPIC_ID BIT_ULL(0)12 #define VALID_CPUID_INFO BIT_ULL(1)29 #define INFO_VALID_CHECK_INFO BIT_ULL(0)30 #define INFO_VALID_TARGET_ID BIT_ULL(1)31 #define INFO_VALID_REQUESTOR_ID BIT_ULL(2)32 #define INFO_VALID_RESPONDER_ID BIT_ULL(3)33 #define INFO_VALID_IP BIT_ULL(4)35 #define CHECK_VALID_TRANS_TYPE BIT_ULL(0)36 #define CHECK_VALID_OPERATION BIT_ULL(1)37 #define CHECK_VALID_LEVEL BIT_ULL(2)[all …]
15 #define RC_PROTO_BIT_UNKNOWN BIT_ULL(RC_PROTO_UNKNOWN)16 #define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER)17 #define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5)18 #define RC_PROTO_BIT_RC5X_20 BIT_ULL(RC_PROTO_RC5X_20)19 #define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ)20 #define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC)21 #define RC_PROTO_BIT_SONY12 BIT_ULL(RC_PROTO_SONY12)22 #define RC_PROTO_BIT_SONY15 BIT_ULL(RC_PROTO_SONY15)23 #define RC_PROTO_BIT_SONY20 BIT_ULL(RC_PROTO_SONY20)24 #define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC)[all …]
33 #define CMR_EN BIT_ULL(55)34 #define DATA_PKT_TX_EN BIT_ULL(53)35 #define DATA_PKT_RX_EN BIT_ULL(54)39 #define FW_CGX_INT BIT_ULL(1)45 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)46 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)47 #define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)48 #define CGX_DMAC_MCAST_MODE BIT_ULL(1)49 #define CGX_DMAC_BCAST_MODE BIT_ULL(0)51 #define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)[all …]
18 #define RPMX_RX_TS_PREPEND BIT_ULL(22)25 #define RPMX_MTI_PCS_LBK BIT_ULL(14)31 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29)32 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28)33 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)34 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19)53 #define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8)54 #define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4)60 #define RPM_TX_EN BIT_ULL(0)61 #define RPM_RX_EN BIT_ULL(1)[all …]
39 #define PIN_NOEVICT BIT_ULL(0)40 #define PIN_NOSEARCH BIT_ULL(1)41 #define PIN_NONBLOCK BIT_ULL(2)42 #define PIN_MAPPABLE BIT_ULL(3)43 #define PIN_ZONE_4G BIT_ULL(4)44 #define PIN_HIGH BIT_ULL(5)45 #define PIN_OFFSET_BIAS BIT_ULL(6)46 #define PIN_OFFSET_FIXED BIT_ULL(7)47 #define PIN_VALIDATE BIT_ULL(8) /* validate placement only, no need to call unpin() */49 #define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */[all …]
303 #define IAVF_FLAG_AQ_ENABLE_QUEUES BIT_ULL(0)304 #define IAVF_FLAG_AQ_DISABLE_QUEUES BIT_ULL(1)305 #define IAVF_FLAG_AQ_ADD_MAC_FILTER BIT_ULL(2)306 #define IAVF_FLAG_AQ_ADD_VLAN_FILTER BIT_ULL(3)307 #define IAVF_FLAG_AQ_DEL_MAC_FILTER BIT_ULL(4)308 #define IAVF_FLAG_AQ_DEL_VLAN_FILTER BIT_ULL(5)309 #define IAVF_FLAG_AQ_CONFIGURE_QUEUES BIT_ULL(6)310 #define IAVF_FLAG_AQ_MAP_VECTORS BIT_ULL(7)311 #define IAVF_FLAG_AQ_HANDLE_RESET BIT_ULL(8)312 #define IAVF_FLAG_AQ_CONFIGURE_RSS BIT_ULL(9) /* direct AQ config */[all …]
56 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV4_SA)58 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV6_SA)60 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV4_DA)62 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV6_DA)64 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_TCP_SRC_PORT)66 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_TCP_DST_PORT)68 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_UDP_SRC_PORT)70 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_UDP_DST_PORT)72 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_SCTP_SRC_PORT)74 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_SCTP_DST_PORT)
367 #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)368 #define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33)369 #define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34)370 #define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35)371 #define CN6XXX_INTR_DMA0_TIME BIT_ULL(36)372 #define CN6XXX_INTR_DMA1_TIME BIT_ULL(37)373 #define CN6XXX_INTR_INSTR_DB_OF_ERR BIT_ULL(48)374 #define CN6XXX_INTR_SLIST_DB_OF_ERR BIT_ULL(49)375 #define CN6XXX_INTR_POUT_ERR BIT_ULL(50)376 #define CN6XXX_INTR_PIN_BP_ERR BIT_ULL(51)[all …]
137 #define CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16)186 #define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)233 #define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62)234 #define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48)389 #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)425 #define CN23XX_INTR_PO_INT BIT_ULL(63)426 #define CN23XX_INTR_PI_INT BIT_ULL(62)427 #define CN23XX_INTR_MBOX_INT BIT_ULL(61)428 #define CN23XX_INTR_RESEND BIT_ULL(60)430 #define CN23XX_INTR_CINT_ENB BIT_ULL(48)[all …]
127 [DEV_USB_OTG] = BIT_ULL(EXTCON_USB_HOST),128 [DEV_DEDICATED_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_DCP),129 [DEV_USB_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),130 [DEV_CAR_KIT] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP)131 | BIT_ULL(EXTCON_JACK_LINE_OUT),132 [DEV_UART] = BIT_ULL(EXTCON_JIG),133 [DEV_USB] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),134 [DEV_AUDIO_2] = BIT_ULL(EXTCON_JACK_LINE_OUT),135 [DEV_AUDIO_1] = BIT_ULL(EXTCON_JACK_LINE_OUT),136 [DEV_AV] = BIT_ULL(EXTCON_JACK_LINE_OUT)[all …]
86 #define TPS_REG_INT_USER_VID_ALT_MODE_OTHER_VDM BIT_ULL(27+32)87 #define TPS_REG_INT_USER_VID_ALT_MODE_ATTN_VDM BIT_ULL(26+32)88 #define TPS_REG_INT_USER_VID_ALT_MODE_EXIT BIT_ULL(25+32)89 #define TPS_REG_INT_USER_VID_ALT_MODE_ENTERED BIT_ULL(24+32)90 #define TPS_REG_INT_EXIT_MODES_COMPLETE BIT_ULL(20+32)91 #define TPS_REG_INT_DISCOVER_MODES_COMPLETE BIT_ULL(19+32)92 #define TPS_REG_INT_VDM_MSG_SENT BIT_ULL(18+32)93 #define TPS_REG_INT_VDM_ENTERED_MODE BIT_ULL(17+32)94 #define TPS_REG_INT_ERROR_UNABLE_TO_SOURCE BIT_ULL(14+32)95 #define TPS_REG_INT_SRC_TRANSITION BIT_ULL(10+32)[all …]
193 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)194 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)195 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)196 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)197 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)198 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)199 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)200 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)201 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)202 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)[all …]
12 #define SW_TWSI_V BIT_ULL(63) /* Valid bit */13 #define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */14 #define SW_TWSI_R BIT_ULL(56) /* Result or read bit */15 #define SW_TWSI_SOVR BIT_ULL(55) /* Size override */77 #define TWSI_INT_ST_INT BIT_ULL(0)78 #define TWSI_INT_TS_INT BIT_ULL(1)79 #define TWSI_INT_CORE_INT BIT_ULL(2)80 #define TWSI_INT_ST_EN BIT_ULL(4)81 #define TWSI_INT_TS_EN BIT_ULL(5)82 #define TWSI_INT_CORE_EN BIT_ULL(6)[all …]