Searched refs:BIT9 (Results 1 – 19 of 19) sorted by relevance
205 #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */234 #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */
26 #define BIT9 0x00000200 macro
556 #define RRSR_36M BIT9706 #define IMR_BDOK BIT9 /* Beacon Queue DMA OK Interrupt */722 #define IMR_C2HCMD BIT9753 #define RCR_AICV BIT9 /* Accept ICV error packet */
53 #define DYNAMIC_BB_RATE_ADAPTIVE BIT9 /* ODM_BB_RATE_ADAPTIVE */
219 #define IMR_BDOK BIT9240 #define TPPoll_StopBK BIT9370 #define RRSR_36M BIT9
40 #define BIT9 0x00000200 macro
101 #define ALGO_TRACE_SW_EXEC BIT9
2631 u16tmp |= BIT9; in btc8192e2ant_init_hwconfig()
394 #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */423 #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */
158 #define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
375 ODM_BB_RATE_ADAPTIVE = BIT9,
22 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
19 #define BIT9 0x00000200 macro
28 #define BIT9 0x0200 macro
67 #define BIT9 0x00000200 macro
390 #define IRQ_RXIDLE BIT9 /* HDLC */391 #define IRQ_RXBREAK BIT9 /* async */4056 val |= BIT9; in async_mode()4096 val |= BIT9; in async_mode()4219 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()4220 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()4292 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()4293 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()4936 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
367 #define RRSR_36M BIT9
777 #define LPFC_SLI4_INTR9 BIT9
296 #define IRQ_TXREPEAT BIT9 // tx message repeat