| /linux-5.19.10/drivers/staging/rtl8723bs/include/ |
| D | hal_pwr_seq.h | 57 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL co…
64 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 int…
75 …{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6…
163 …{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6…
212 …PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW in…
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| D | hal_com_reg.h | 526 #define HSISR_RON_INT BIT6
553 #define RRSR_12M BIT6
709 #define IMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */
756 #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */
1284 #define SDIO_HIMR_TXBCNOK_MSK BIT6
1306 #define SDIO_HISR_TXBCNOK BIT6
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| D | rtl8723b_spec.h | 208 #define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */
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| D | osdep_service.h | 23 #define BIT6 0x00000040 macro
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| /linux-5.19.10/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_hw.h | 222 #define IMR_MGNTDOK BIT6
237 #define TPPoll_MQ BIT6
277 #define AcmHw_VoqStatus BIT6
367 #define RRSR_12M BIT6
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| /linux-5.19.10/drivers/video/fbdev/via/ |
| D | lcd.c | 376 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
609 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
618 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
631 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); in integrated_lvds_disable()
637 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
661 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
670 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
686 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); in integrated_lvds_enable()
692 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
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| D | dvi.c | 55 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
62 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
421 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
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| D | hw.c | 1669 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1676 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1680 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
2033 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2035 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in enable_second_display_channel()
2041 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2043 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in disable_second_display_channel()
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| D | share.h | 20 #define BIT6 0x40 macro
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| /linux-5.19.10/drivers/scsi/ |
| D | dc395x.h | 70 #define BIT6 0x00000040 macro
138 #define DATAIN BIT6
171 #define EN_ATN_STOP BIT6
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| /linux-5.19.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 37 #define BIT6 0x00000040 macro
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| D | halbtc8821a1ant.h | 9 #define BT_INFO_8821A_1ANT_B_A2DP BIT6
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| D | halbtc8192e2ant.h | 8 #define BT_INFO_8192E_2ANT_B_A2DP BIT6
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| D | halbtc8821a2ant.h | 9 #define BT_INFO_8821A_2ANT_B_A2DP BIT6
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| D | halbtc8723b2ant.h | 11 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
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| /linux-5.19.10/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
| D | pwrseq.h | 285 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
420 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
444 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
642 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
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| /linux-5.19.10/drivers/char/pcmcia/ |
| D | synclink_cs.c | 299 #define IRQ_EXITHUNT BIT6 // receive frame start
300 #define IRQ_RXTIME BIT6 // rx char timeout
307 #define XFW BIT6 // transmit FIFO write enable
677 #define CMD_RXRESET BIT6 // receiver reset
925 if (status & (BIT7 | BIT6)) { in rx_ready_async()
939 else if (status & BIT6) in rx_ready_async()
1470 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1472 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
2178 set_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
2180 clear_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
[all …]
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| /linux-5.19.10/drivers/net/hamradio/ |
| D | z8530.h | 118 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-5.19.10/drivers/tty/serial/ |
| D | zs.h | 173 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| D | ip22zilog.h | 154 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| D | sunzilog.h | 156 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-5.19.10/drivers/staging/rtl8723bs/hal/ |
| D | HalHWImg8723B_MAC.c | 19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
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| D | HalBtc8723b2Ant.h | 9 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
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| D | HalBtc8723b1Ant.h | 9 #define BT_INFO_8723B_1ANT_B_A2DP BIT6
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| /linux-5.19.10/drivers/staging/rtl8192e/ |
| D | rtl819x_Qos.h | 16 #define BIT6 0x00000040 macro
|