1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Header file for the Atmel AHB DMA Controller driver
4  *
5  * Copyright (C) 2008 Atmel Corporation
6  */
7 #ifndef AT_HDMAC_REGS_H
8 #define	AT_HDMAC_REGS_H
9 
10 #define	AT_DMA_MAX_NR_CHANNELS	8
11 
12 
13 #define	AT_DMA_GCFG	0x00	/* Global Configuration Register */
14 #define		AT_DMA_IF_BIGEND(i)	(0x1 << (i))	/* AHB-Lite Interface i in Big-endian mode */
15 #define		AT_DMA_ARB_CFG	(0x1 << 4)	/* Arbiter mode. */
16 #define			AT_DMA_ARB_CFG_FIXED		(0x0 << 4)
17 #define			AT_DMA_ARB_CFG_ROUND_ROBIN	(0x1 << 4)
18 
19 #define	AT_DMA_EN	0x04	/* Controller Enable Register */
20 #define		AT_DMA_ENABLE	(0x1 << 0)
21 
22 #define	AT_DMA_SREQ	0x08	/* Software Single Request Register */
23 #define		AT_DMA_SSREQ(x)	(0x1 << ((x) << 1))		/* Request a source single transfer on channel x */
24 #define		AT_DMA_DSREQ(x)	(0x1 << (1 + ((x) << 1)))	/* Request a destination single transfer on channel x */
25 
26 #define	AT_DMA_CREQ	0x0C	/* Software Chunk Transfer Request Register */
27 #define		AT_DMA_SCREQ(x)	(0x1 << ((x) << 1))		/* Request a source chunk transfer on channel x */
28 #define		AT_DMA_DCREQ(x)	(0x1 << (1 + ((x) << 1)))	/* Request a destination chunk transfer on channel x */
29 
30 #define	AT_DMA_LAST	0x10	/* Software Last Transfer Flag Register */
31 #define		AT_DMA_SLAST(x)	(0x1 << ((x) << 1))		/* This src rq is last tx of buffer on channel x */
32 #define		AT_DMA_DLAST(x)	(0x1 << (1 + ((x) << 1)))	/* This dst rq is last tx of buffer on channel x */
33 
34 #define	AT_DMA_SYNC	0x14	/* Request Synchronization Register */
35 #define		AT_DMA_SYR(h)	(0x1 << (h))			/* Synchronize handshake line h */
36 
37 /* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
38 #define	AT_DMA_EBCIER	0x18	/* Enable register */
39 #define	AT_DMA_EBCIDR	0x1C	/* Disable register */
40 #define	AT_DMA_EBCIMR	0x20	/* Mask Register */
41 #define	AT_DMA_EBCISR	0x24	/* Status Register */
42 #define		AT_DMA_CBTC_OFFSET	8
43 #define		AT_DMA_ERR_OFFSET	16
44 #define		AT_DMA_BTC(x)	(0x1 << (x))
45 #define		AT_DMA_CBTC(x)	(0x1 << (AT_DMA_CBTC_OFFSET + (x)))
46 #define		AT_DMA_ERR(x)	(0x1 << (AT_DMA_ERR_OFFSET + (x)))
47 
48 #define	AT_DMA_CHER	0x28	/* Channel Handler Enable Register */
49 #define		AT_DMA_ENA(x)	(0x1 << (x))
50 #define		AT_DMA_SUSP(x)	(0x1 << ( 8 + (x)))
51 #define		AT_DMA_KEEP(x)	(0x1 << (24 + (x)))
52 
53 #define	AT_DMA_CHDR	0x2C	/* Channel Handler Disable Register */
54 #define		AT_DMA_DIS(x)	(0x1 << (x))
55 #define		AT_DMA_RES(x)	(0x1 << ( 8 + (x)))
56 
57 #define	AT_DMA_CHSR	0x30	/* Channel Handler Status Register */
58 #define		AT_DMA_EMPT(x)	(0x1 << (16 + (x)))
59 #define		AT_DMA_STAL(x)	(0x1 << (24 + (x)))
60 
61 
62 #define	AT_DMA_CH_REGS_BASE	0x3C	/* Channel registers base address */
63 #define	ch_regs(x)	(AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
64 
65 /* Hardware register offset for each channel */
66 #define	ATC_SADDR_OFFSET	0x00	/* Source Address Register */
67 #define	ATC_DADDR_OFFSET	0x04	/* Destination Address Register */
68 #define	ATC_DSCR_OFFSET		0x08	/* Descriptor Address Register */
69 #define	ATC_CTRLA_OFFSET	0x0C	/* Control A Register */
70 #define	ATC_CTRLB_OFFSET	0x10	/* Control B Register */
71 #define	ATC_CFG_OFFSET		0x14	/* Configuration Register */
72 #define	ATC_SPIP_OFFSET		0x18	/* Src PIP Configuration Register */
73 #define	ATC_DPIP_OFFSET		0x1C	/* Dst PIP Configuration Register */
74 
75 
76 /* Bitfield definitions */
77 
78 /* Bitfields in DSCR */
79 #define	ATC_DSCR_IF(i)		(0x3 & (i))	/* Dsc feched via AHB-Lite Interface i */
80 
81 /* Bitfields in CTRLA */
82 #define	ATC_BTSIZE_MAX		0xFFFFUL	/* Maximum Buffer Transfer Size */
83 #define	ATC_BTSIZE(x)		(ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
84 #define	ATC_SCSIZE_MASK		(0x7 << 16)	/* Source Chunk Transfer Size */
85 #define		ATC_SCSIZE(x)		(ATC_SCSIZE_MASK & ((x) << 16))
86 #define		ATC_SCSIZE_1		(0x0 << 16)
87 #define		ATC_SCSIZE_4		(0x1 << 16)
88 #define		ATC_SCSIZE_8		(0x2 << 16)
89 #define		ATC_SCSIZE_16		(0x3 << 16)
90 #define		ATC_SCSIZE_32		(0x4 << 16)
91 #define		ATC_SCSIZE_64		(0x5 << 16)
92 #define		ATC_SCSIZE_128		(0x6 << 16)
93 #define		ATC_SCSIZE_256		(0x7 << 16)
94 #define	ATC_DCSIZE_MASK		(0x7 << 20)	/* Destination Chunk Transfer Size */
95 #define		ATC_DCSIZE(x)		(ATC_DCSIZE_MASK & ((x) << 20))
96 #define		ATC_DCSIZE_1		(0x0 << 20)
97 #define		ATC_DCSIZE_4		(0x1 << 20)
98 #define		ATC_DCSIZE_8		(0x2 << 20)
99 #define		ATC_DCSIZE_16		(0x3 << 20)
100 #define		ATC_DCSIZE_32		(0x4 << 20)
101 #define		ATC_DCSIZE_64		(0x5 << 20)
102 #define		ATC_DCSIZE_128		(0x6 << 20)
103 #define		ATC_DCSIZE_256		(0x7 << 20)
104 #define	ATC_SRC_WIDTH_MASK	(0x3 << 24)	/* Source Single Transfer Size */
105 #define		ATC_SRC_WIDTH(x)	((x) << 24)
106 #define		ATC_SRC_WIDTH_BYTE	(0x0 << 24)
107 #define		ATC_SRC_WIDTH_HALFWORD	(0x1 << 24)
108 #define		ATC_SRC_WIDTH_WORD	(0x2 << 24)
109 #define		ATC_REG_TO_SRC_WIDTH(r)	(((r) >> 24) & 0x3)
110 #define	ATC_DST_WIDTH_MASK	(0x3 << 28)	/* Destination Single Transfer Size */
111 #define		ATC_DST_WIDTH(x)	((x) << 28)
112 #define		ATC_DST_WIDTH_BYTE	(0x0 << 28)
113 #define		ATC_DST_WIDTH_HALFWORD	(0x1 << 28)
114 #define		ATC_DST_WIDTH_WORD	(0x2 << 28)
115 #define	ATC_DONE		(0x1 << 31)	/* Tx Done (only written back in descriptor) */
116 
117 /* Bitfields in CTRLB */
118 #define	ATC_SIF(i)		(0x3 & (i))	/* Src tx done via AHB-Lite Interface i */
119 #define	ATC_DIF(i)		((0x3 & (i)) <<  4)	/* Dst tx done via AHB-Lite Interface i */
120 				  /* Specify AHB interfaces */
121 #define AT_DMA_MEM_IF		0 /* interface 0 as memory interface */
122 #define AT_DMA_PER_IF		1 /* interface 1 as peripheral interface */
123 
124 #define	ATC_SRC_PIP		(0x1 <<  8)	/* Source Picture-in-Picture enabled */
125 #define	ATC_DST_PIP		(0x1 << 12)	/* Destination Picture-in-Picture enabled */
126 #define	ATC_SRC_DSCR_DIS	(0x1 << 16)	/* Src Descriptor fetch disable */
127 #define	ATC_DST_DSCR_DIS	(0x1 << 20)	/* Dst Descriptor fetch disable */
128 #define	ATC_FC_MASK		(0x7 << 21)	/* Choose Flow Controller */
129 #define		ATC_FC_MEM2MEM		(0x0 << 21)	/* Mem-to-Mem (DMA) */
130 #define		ATC_FC_MEM2PER		(0x1 << 21)	/* Mem-to-Periph (DMA) */
131 #define		ATC_FC_PER2MEM		(0x2 << 21)	/* Periph-to-Mem (DMA) */
132 #define		ATC_FC_PER2PER		(0x3 << 21)	/* Periph-to-Periph (DMA) */
133 #define		ATC_FC_PER2MEM_PER	(0x4 << 21)	/* Periph-to-Mem (Peripheral) */
134 #define		ATC_FC_MEM2PER_PER	(0x5 << 21)	/* Mem-to-Periph (Peripheral) */
135 #define		ATC_FC_PER2PER_SRCPER	(0x6 << 21)	/* Periph-to-Periph (Src Peripheral) */
136 #define		ATC_FC_PER2PER_DSTPER	(0x7 << 21)	/* Periph-to-Periph (Dst Peripheral) */
137 #define	ATC_SRC_ADDR_MODE_MASK	(0x3 << 24)
138 #define		ATC_SRC_ADDR_MODE_INCR	(0x0 << 24)	/* Incrementing Mode */
139 #define		ATC_SRC_ADDR_MODE_DECR	(0x1 << 24)	/* Decrementing Mode */
140 #define		ATC_SRC_ADDR_MODE_FIXED	(0x2 << 24)	/* Fixed Mode */
141 #define	ATC_DST_ADDR_MODE_MASK	(0x3 << 28)
142 #define		ATC_DST_ADDR_MODE_INCR	(0x0 << 28)	/* Incrementing Mode */
143 #define		ATC_DST_ADDR_MODE_DECR	(0x1 << 28)	/* Decrementing Mode */
144 #define		ATC_DST_ADDR_MODE_FIXED	(0x2 << 28)	/* Fixed Mode */
145 #define	ATC_IEN			(0x1 << 30)	/* BTC interrupt enable (active low) */
146 #define	ATC_AUTO		(0x1 << 31)	/* Auto multiple buffer tx enable */
147 
148 /* Bitfields in CFG */
149 #define ATC_PER_MSB(h)	((0x30U & (h)) >> 4)	/* Extract most significant bits of a handshaking identifier */
150 
151 #define	ATC_SRC_PER(h)		(0xFU & (h))	/* Channel src rq associated with periph handshaking ifc h */
152 #define	ATC_DST_PER(h)		((0xFU & (h)) <<  4)	/* Channel dst rq associated with periph handshaking ifc h */
153 #define	ATC_SRC_REP		(0x1 <<  8)	/* Source Replay Mod */
154 #define	ATC_SRC_H2SEL		(0x1 <<  9)	/* Source Handshaking Mod */
155 #define		ATC_SRC_H2SEL_SW	(0x0 <<  9)
156 #define		ATC_SRC_H2SEL_HW	(0x1 <<  9)
157 #define	ATC_SRC_PER_MSB(h)	(ATC_PER_MSB(h) << 10)	/* Channel src rq (most significant bits) */
158 #define	ATC_DST_REP		(0x1 << 12)	/* Destination Replay Mod */
159 #define	ATC_DST_H2SEL		(0x1 << 13)	/* Destination Handshaking Mod */
160 #define		ATC_DST_H2SEL_SW	(0x0 << 13)
161 #define		ATC_DST_H2SEL_HW	(0x1 << 13)
162 #define	ATC_DST_PER_MSB(h)	(ATC_PER_MSB(h) << 14)	/* Channel dst rq (most significant bits) */
163 #define	ATC_SOD			(0x1 << 16)	/* Stop On Done */
164 #define	ATC_LOCK_IF		(0x1 << 20)	/* Interface Lock */
165 #define	ATC_LOCK_B		(0x1 << 21)	/* AHB Bus Lock */
166 #define	ATC_LOCK_IF_L		(0x1 << 22)	/* Master Interface Arbiter Lock */
167 #define		ATC_LOCK_IF_L_CHUNK	(0x0 << 22)
168 #define		ATC_LOCK_IF_L_BUFFER	(0x1 << 22)
169 #define	ATC_AHB_PROT_MASK	(0x7 << 24)	/* AHB Protection */
170 #define	ATC_FIFOCFG_MASK	(0x3 << 28)	/* FIFO Request Configuration */
171 #define		ATC_FIFOCFG_LARGESTBURST	(0x0 << 28)
172 #define		ATC_FIFOCFG_HALFFIFO		(0x1 << 28)
173 #define		ATC_FIFOCFG_ENOUGHSPACE		(0x2 << 28)
174 
175 /* Bitfields in SPIP */
176 #define	ATC_SPIP_HOLE(x)	(0xFFFFU & (x))
177 #define	ATC_SPIP_BOUNDARY(x)	((0x3FF & (x)) << 16)
178 
179 /* Bitfields in DPIP */
180 #define	ATC_DPIP_HOLE(x)	(0xFFFFU & (x))
181 #define	ATC_DPIP_BOUNDARY(x)	((0x3FF & (x)) << 16)
182 
183 
184 /*--  descriptors  -----------------------------------------------------*/
185 
186 /* LLI == Linked List Item; aka DMA buffer descriptor */
187 struct at_lli {
188 	/* values that are not changed by hardware */
189 	dma_addr_t	saddr;
190 	dma_addr_t	daddr;
191 	/* value that may get written back: */
192 	u32		ctrla;
193 	/* more values that are not changed by hardware */
194 	u32		ctrlb;
195 	dma_addr_t	dscr;	/* chain to next lli */
196 };
197 
198 /**
199  * struct at_desc - software descriptor
200  * @at_lli: hardware lli structure
201  * @txd: support for the async_tx api
202  * @desc_node: node on the channed descriptors list
203  * @len: descriptor byte count
204  * @total_len: total transaction byte count
205  */
206 struct at_desc {
207 	/* FIRST values the hardware uses */
208 	struct at_lli			lli;
209 
210 	/* THEN values for driver housekeeping */
211 	struct list_head		tx_list;
212 	struct dma_async_tx_descriptor	txd;
213 	struct list_head		desc_node;
214 	size_t				len;
215 	size_t				total_len;
216 
217 	/* Interleaved data */
218 	size_t				boundary;
219 	size_t				dst_hole;
220 	size_t				src_hole;
221 
222 	/* Memset temporary buffer */
223 	bool				memset_buffer;
224 	dma_addr_t			memset_paddr;
225 	int				*memset_vaddr;
226 };
227 
228 static inline struct at_desc *
txd_to_at_desc(struct dma_async_tx_descriptor * txd)229 txd_to_at_desc(struct dma_async_tx_descriptor *txd)
230 {
231 	return container_of(txd, struct at_desc, txd);
232 }
233 
234 
235 /*--  Channels  --------------------------------------------------------*/
236 
237 /**
238  * atc_status - information bits stored in channel status flag
239  *
240  * Manipulated with atomic operations.
241  */
242 enum atc_status {
243 	ATC_IS_ERROR = 0,
244 	ATC_IS_PAUSED = 1,
245 	ATC_IS_CYCLIC = 24,
246 };
247 
248 /**
249  * struct at_dma_chan - internal representation of an Atmel HDMAC channel
250  * @chan_common: common dmaengine channel object members
251  * @device: parent device
252  * @ch_regs: memory mapped register base
253  * @mask: channel index in a mask
254  * @per_if: peripheral interface
255  * @mem_if: memory interface
256  * @status: transmit status information from irq/prep* functions
257  *                to tasklet (use atomic operations)
258  * @tasklet: bottom half to finish transaction work
259  * @save_cfg: configuration register that is saved on suspend/resume cycle
260  * @save_dscr: for cyclic operations, preserve next descriptor address in
261  *             the cyclic list on suspend/resume cycle
262  * @dma_sconfig: configuration for slave transfers, passed via
263  * .device_config
264  * @lock: serializes enqueue/dequeue operations to descriptors lists
265  * @active_list: list of descriptors dmaengine is being running on
266  * @queue: list of descriptors ready to be submitted to engine
267  * @free_list: list of descriptors usable by the channel
268  */
269 struct at_dma_chan {
270 	struct dma_chan		chan_common;
271 	struct at_dma		*device;
272 	void __iomem		*ch_regs;
273 	u8			mask;
274 	u8			per_if;
275 	u8			mem_if;
276 	unsigned long		status;
277 	struct tasklet_struct	tasklet;
278 	u32			save_cfg;
279 	u32			save_dscr;
280 	struct dma_slave_config dma_sconfig;
281 
282 	spinlock_t		lock;
283 
284 	/* these other elements are all protected by lock */
285 	struct list_head	active_list;
286 	struct list_head	queue;
287 	struct list_head	free_list;
288 };
289 
290 #define	channel_readl(atchan, name) \
291 	__raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
292 
293 #define	channel_writel(atchan, name, val) \
294 	__raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
295 
to_at_dma_chan(struct dma_chan * dchan)296 static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
297 {
298 	return container_of(dchan, struct at_dma_chan, chan_common);
299 }
300 
301 /*
302  * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
303  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
304  *
305  * This can be done by finding most significant bit set.
306  */
convert_burst(u32 * maxburst)307 static inline void convert_burst(u32 *maxburst)
308 {
309 	if (*maxburst > 1)
310 		*maxburst = fls(*maxburst) - 2;
311 	else
312 		*maxburst = 0;
313 }
314 
315 /*
316  * Fix sconfig's bus width according to at_hdmac.
317  * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
318  */
convert_buswidth(enum dma_slave_buswidth addr_width)319 static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
320 {
321 	switch (addr_width) {
322 	case DMA_SLAVE_BUSWIDTH_2_BYTES:
323 		return 1;
324 	case DMA_SLAVE_BUSWIDTH_4_BYTES:
325 		return 2;
326 	default:
327 		/* For 1 byte width or fallback */
328 		return 0;
329 	}
330 }
331 
332 /*--  Controller  ------------------------------------------------------*/
333 
334 /**
335  * struct at_dma - internal representation of an Atmel HDMA Controller
336  * @chan_common: common dmaengine dma_device object members
337  * @atdma_devtype: identifier of DMA controller compatibility
338  * @ch_regs: memory mapped register base
339  * @clk: dma controller clock
340  * @save_imr: interrupt mask register that is saved on suspend/resume cycle
341  * @all_chan_mask: all channels availlable in a mask
342  * @dma_desc_pool: base of DMA descriptor region (DMA address)
343  * @chan: channels table to store at_dma_chan structures
344  */
345 struct at_dma {
346 	struct dma_device	dma_common;
347 	void __iomem		*regs;
348 	struct clk		*clk;
349 	u32			save_imr;
350 
351 	u8			all_chan_mask;
352 
353 	struct dma_pool		*dma_desc_pool;
354 	struct dma_pool		*memset_pool;
355 	/* AT THE END channels table */
356 	struct at_dma_chan	chan[];
357 };
358 
359 #define	dma_readl(atdma, name) \
360 	__raw_readl((atdma)->regs + AT_DMA_##name)
361 #define	dma_writel(atdma, name, val) \
362 	__raw_writel((val), (atdma)->regs + AT_DMA_##name)
363 
to_at_dma(struct dma_device * ddev)364 static inline struct at_dma *to_at_dma(struct dma_device *ddev)
365 {
366 	return container_of(ddev, struct at_dma, dma_common);
367 }
368 
369 
370 /*--  Helper functions  ------------------------------------------------*/
371 
chan2dev(struct dma_chan * chan)372 static struct device *chan2dev(struct dma_chan *chan)
373 {
374 	return &chan->dev->device;
375 }
376 
377 #if defined(VERBOSE_DEBUG)
vdbg_dump_regs(struct at_dma_chan * atchan)378 static void vdbg_dump_regs(struct at_dma_chan *atchan)
379 {
380 	struct at_dma	*atdma = to_at_dma(atchan->chan_common.device);
381 
382 	dev_err(chan2dev(&atchan->chan_common),
383 		"  channel %d : imr = 0x%x, chsr = 0x%x\n",
384 		atchan->chan_common.chan_id,
385 		dma_readl(atdma, EBCIMR),
386 		dma_readl(atdma, CHSR));
387 
388 	dev_err(chan2dev(&atchan->chan_common),
389 		"  channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
390 		channel_readl(atchan, SADDR),
391 		channel_readl(atchan, DADDR),
392 		channel_readl(atchan, CTRLA),
393 		channel_readl(atchan, CTRLB),
394 		channel_readl(atchan, CFG),
395 		channel_readl(atchan, DSCR));
396 }
397 #else
vdbg_dump_regs(struct at_dma_chan * atchan)398 static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
399 #endif
400 
atc_dump_lli(struct at_dma_chan * atchan,struct at_lli * lli)401 static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
402 {
403 	dev_crit(chan2dev(&atchan->chan_common),
404 		 "desc: s%pad d%pad ctrl0x%x:0x%x l%pad\n",
405 		 &lli->saddr, &lli->daddr,
406 		 lli->ctrla, lli->ctrlb, &lli->dscr);
407 }
408 
409 
atc_setup_irq(struct at_dma * atdma,int chan_id,int on)410 static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
411 {
412 	u32 ebci;
413 
414 	/* enable interrupts on buffer transfer completion & error */
415 	ebci =    AT_DMA_BTC(chan_id)
416 		| AT_DMA_ERR(chan_id);
417 	if (on)
418 		dma_writel(atdma, EBCIER, ebci);
419 	else
420 		dma_writel(atdma, EBCIDR, ebci);
421 }
422 
atc_enable_chan_irq(struct at_dma * atdma,int chan_id)423 static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
424 {
425 	atc_setup_irq(atdma, chan_id, 1);
426 }
427 
atc_disable_chan_irq(struct at_dma * atdma,int chan_id)428 static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
429 {
430 	atc_setup_irq(atdma, chan_id, 0);
431 }
432 
433 
434 /**
435  * atc_chan_is_enabled - test if given channel is enabled
436  * @atchan: channel we want to test status
437  */
atc_chan_is_enabled(struct at_dma_chan * atchan)438 static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
439 {
440 	struct at_dma	*atdma = to_at_dma(atchan->chan_common.device);
441 
442 	return !!(dma_readl(atdma, CHSR) & atchan->mask);
443 }
444 
445 /**
446  * atc_chan_is_paused - test channel pause/resume status
447  * @atchan: channel we want to test status
448  */
atc_chan_is_paused(struct at_dma_chan * atchan)449 static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
450 {
451 	return test_bit(ATC_IS_PAUSED, &atchan->status);
452 }
453 
454 /**
455  * atc_chan_is_cyclic - test if given channel has cyclic property set
456  * @atchan: channel we want to test status
457  */
atc_chan_is_cyclic(struct at_dma_chan * atchan)458 static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
459 {
460 	return test_bit(ATC_IS_CYCLIC, &atchan->status);
461 }
462 
463 /**
464  * set_desc_eol - set end-of-link to descriptor so it will end transfer
465  * @desc: descriptor, signle or at the end of a chain, to end chain on
466  */
set_desc_eol(struct at_desc * desc)467 static void set_desc_eol(struct at_desc *desc)
468 {
469 	u32 ctrlb = desc->lli.ctrlb;
470 
471 	ctrlb &= ~ATC_IEN;
472 	ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
473 
474 	desc->lli.ctrlb = ctrlb;
475 	desc->lli.dscr = 0;
476 }
477 
478 #endif /* AT_HDMAC_REGS_H */
479