1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef MAC_H
18 #define MAC_H
19 #include <net/cfg80211.h>
20 
21 #define set11nTries(_series, _index) \
22 	(SM((_series)[_index].Tries, AR_XmitDataTries##_index))
23 
24 #define set11nRate(_series, _index) \
25 	(SM((_series)[_index].Rate, AR_XmitRate##_index))
26 
27 #define set11nPktDurRTSCTS(_series, _index)				\
28 	(SM((_series)[_index].PktDuration, AR_PacketDur##_index) |	\
29 	 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS   ?	\
30 	  AR_RTSCTSQual##_index : 0))
31 
32 #define set11nRateFlags(_series, _index)				\
33 	(((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ?		\
34 	  AR_2040_##_index : 0)						\
35 	 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ?	\
36 	   AR_GI##_index : 0)						\
37 	 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ?	\
38 	   AR_STBC##_index : 0))
39 
40 #define set11nChainSel(_series, _index)					\
41 	(SM((_series)[_index].ChSel, AR_ChainSel##_index))
42 
43 #define CCK_SIFS_TIME        10
44 #define CCK_PREAMBLE_BITS   144
45 #define CCK_PLCP_BITS        48
46 
47 #define OFDM_SIFS_TIME        16
48 #define OFDM_PREAMBLE_TIME    20
49 #define OFDM_PLCP_BITS        22
50 #define OFDM_SYMBOL_TIME      4
51 
52 #define OFDM_SIFS_TIME_HALF     32
53 #define OFDM_PREAMBLE_TIME_HALF 40
54 #define OFDM_PLCP_BITS_HALF     22
55 #define OFDM_SYMBOL_TIME_HALF   8
56 
57 #define OFDM_SIFS_TIME_QUARTER      64
58 #define OFDM_PREAMBLE_TIME_QUARTER  80
59 #define OFDM_PLCP_BITS_QUARTER      22
60 #define OFDM_SYMBOL_TIME_QUARTER    16
61 
62 #define INIT_AIFS       2
63 #define INIT_CWMIN      15
64 #define INIT_CWMIN_11B  31
65 #define INIT_CWMAX      1023
66 #define INIT_SH_RETRY   10
67 #define INIT_LG_RETRY   10
68 #define INIT_SSH_RETRY  32
69 #define INIT_SLG_RETRY  32
70 
71 #define ATH9K_TXERR_XRETRY         0x01
72 #define ATH9K_TXERR_FILT           0x02
73 #define ATH9K_TXERR_FIFO           0x04
74 #define ATH9K_TXERR_XTXOP          0x08
75 #define ATH9K_TXERR_TIMER_EXPIRED  0x10
76 #define ATH9K_TX_ACKED		   0x20
77 #define ATH9K_TX_FLUSH		   0x40
78 #define ATH9K_TXERR_MASK						\
79 	(ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO |	\
80 	 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED | ATH9K_TX_FLUSH)
81 
82 #define ATH9K_TX_BA                0x01
83 #define ATH9K_TX_PWRMGMT           0x02
84 #define ATH9K_TX_DESC_CFG_ERR      0x04
85 #define ATH9K_TX_DATA_UNDERRUN     0x08
86 #define ATH9K_TX_DELIM_UNDERRUN    0x10
87 #define ATH9K_TX_SW_FILTERED       0x80
88 
89 /* 64 bytes */
90 #define MIN_TX_FIFO_THRESHOLD   0x1
91 
92 /*
93  * Single stream device AR9285 and AR9271 require 2 KB
94  * to work around a hardware issue, all other devices
95  * have can use the max 4 KB limit.
96  */
97 #define MAX_TX_FIFO_THRESHOLD   ((4096 / 64) - 1)
98 
99 struct ath_tx_status {
100 	u32 ts_tstamp;
101 	u16 ts_seqnum;
102 	u8 ts_status;
103 	u8 ts_rateindex;
104 	int8_t ts_rssi;
105 	u8 ts_shortretry;
106 	u8 ts_longretry;
107 	u8 ts_virtcol;
108 	u8 ts_flags;
109 	int8_t ts_rssi_ctl0;
110 	int8_t ts_rssi_ctl1;
111 	int8_t ts_rssi_ctl2;
112 	int8_t ts_rssi_ext0;
113 	int8_t ts_rssi_ext1;
114 	int8_t ts_rssi_ext2;
115 	u8 qid;
116 	u16 desc_id;
117 	u8 tid;
118 	u32 ba_low;
119 	u32 ba_high;
120 	u32 evm0;
121 	u32 evm1;
122 	u32 evm2;
123 	u32 duration;
124 };
125 
126 struct ath_rx_status {
127 	u32 rs_tstamp;
128 	u16 rs_datalen;
129 	u8 rs_status;
130 	u8 rs_phyerr;
131 	int8_t rs_rssi;
132 	u8 rs_keyix;
133 	u8 rs_rate;
134 	u8 rs_antenna;
135 	u8 rs_more;
136 	int8_t rs_rssi_ctl[3];
137 	int8_t rs_rssi_ext[3];
138 	u8 rs_isaggr;
139 	u8 rs_firstaggr;
140 	u8 rs_moreaggr;
141 	u8 rs_num_delims;
142 	u8 rs_flags;
143 	bool is_mybeacon;
144 	u32 evm0;
145 	u32 evm1;
146 	u32 evm2;
147 	u32 evm3;
148 	u32 evm4;
149 	u16 enc_flags;
150 	enum rate_info_bw bw;
151 };
152 
153 struct ath_htc_rx_status {
154 	__be64 rs_tstamp;
155 	__be16 rs_datalen;
156 	u8 rs_status;
157 	u8 rs_phyerr;
158 	int8_t rs_rssi;
159 	int8_t rs_rssi_ctl[3];
160 	int8_t rs_rssi_ext[3];
161 	u8 rs_keyix;
162 	u8 rs_rate;
163 	u8 rs_antenna;
164 	u8 rs_more;
165 	u8 rs_isaggr;
166 	u8 rs_moreaggr;
167 	u8 rs_num_delims;
168 	u8 rs_flags;
169 	u8 rs_dummy;
170 	/* FIXME: evm* never used? */
171 	__be32 evm0;
172 	__be32 evm1;
173 	__be32 evm2;
174 };
175 
176 #define ATH9K_RXERR_CRC           0x01
177 #define ATH9K_RXERR_PHY           0x02
178 #define ATH9K_RXERR_FIFO          0x04
179 #define ATH9K_RXERR_DECRYPT       0x08
180 #define ATH9K_RXERR_MIC           0x10
181 #define ATH9K_RXERR_KEYMISS       0x20
182 #define ATH9K_RXERR_CORRUPT_DESC  0x40
183 
184 #define ATH9K_RX_MORE             0x01
185 #define ATH9K_RX_MORE_AGGR        0x02
186 #define ATH9K_RX_GI               0x04
187 #define ATH9K_RX_2040             0x08
188 #define ATH9K_RX_DELIM_CRC_PRE    0x10
189 #define ATH9K_RX_DELIM_CRC_POST   0x20
190 #define ATH9K_RX_DECRYPT_BUSY     0x40
191 
192 #define ATH9K_RXKEYIX_INVALID	((u8)-1)
193 #define ATH9K_TXKEYIX_INVALID	((u8)-1)
194 
195 enum ath9k_phyerr {
196 	ATH9K_PHYERR_UNDERRUN             = 0,  /* Transmit underrun */
197 	ATH9K_PHYERR_TIMING               = 1,  /* Timing error */
198 	ATH9K_PHYERR_PARITY               = 2,  /* Illegal parity */
199 	ATH9K_PHYERR_RATE                 = 3,  /* Illegal rate */
200 	ATH9K_PHYERR_LENGTH               = 4,  /* Illegal length */
201 	ATH9K_PHYERR_RADAR                = 5,  /* Radar detect */
202 	ATH9K_PHYERR_SERVICE              = 6,  /* Illegal service */
203 	ATH9K_PHYERR_TOR                  = 7,  /* Transmit override receive */
204 
205 	ATH9K_PHYERR_OFDM_TIMING          = 17,
206 	ATH9K_PHYERR_OFDM_SIGNAL_PARITY   = 18,
207 	ATH9K_PHYERR_OFDM_RATE_ILLEGAL    = 19,
208 	ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL  = 20,
209 	ATH9K_PHYERR_OFDM_POWER_DROP      = 21,
210 	ATH9K_PHYERR_OFDM_SERVICE         = 22,
211 	ATH9K_PHYERR_OFDM_RESTART         = 23,
212 
213 	ATH9K_PHYERR_CCK_BLOCKER          = 24,
214 	ATH9K_PHYERR_CCK_TIMING           = 25,
215 	ATH9K_PHYERR_CCK_HEADER_CRC       = 26,
216 	ATH9K_PHYERR_CCK_RATE_ILLEGAL     = 27,
217 	ATH9K_PHYERR_CCK_LENGTH_ILLEGAL   = 28,
218 	ATH9K_PHYERR_CCK_POWER_DROP       = 29,
219 	ATH9K_PHYERR_CCK_SERVICE          = 30,
220 	ATH9K_PHYERR_CCK_RESTART          = 31,
221 
222 	ATH9K_PHYERR_HT_CRC_ERROR         = 32,
223 	ATH9K_PHYERR_HT_LENGTH_ILLEGAL    = 33,
224 	ATH9K_PHYERR_HT_RATE_ILLEGAL      = 34,
225 	ATH9K_PHYERR_HT_ZLF               = 35,
226 
227 	ATH9K_PHYERR_FALSE_RADAR_EXT      = 36,
228 	ATH9K_PHYERR_GREEN_FIELD          = 37,
229 	ATH9K_PHYERR_SPECTRAL             = 38,
230 
231 	ATH9K_PHYERR_MAX                  = 39,
232 };
233 
234 struct ath_desc {
235 	u32 ds_link;
236 	u32 ds_data;
237 	u32 ds_ctl0;
238 	u32 ds_ctl1;
239 	u32 ds_hw[20];
240 	void *ds_vdata;
241 } __packed __aligned(4);
242 
243 #define ATH9K_TXDESC_NOACK		0x0002
244 #define ATH9K_TXDESC_RTSENA		0x0004
245 #define ATH9K_TXDESC_CTSENA		0x0008
246 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
247  * the descriptor its marked on.  We take a tx interrupt to reap
248  * descriptors when the h/w hits an EOL condition or
249  * when the descriptor is specifically marked to generate
250  * an interrupt with this flag. Descriptors should be
251  * marked periodically to insure timely replenishing of the
252  * supply needed for sending frames. Defering interrupts
253  * reduces system load and potentially allows more concurrent
254  * work to be done but if done to aggressively can cause
255  * senders to backup. When the hardware queue is left too
256  * large rate control information may also be too out of
257  * date. An Alternative for this is TX interrupt mitigation
258  * but this needs more testing. */
259 #define ATH9K_TXDESC_INTREQ		0x0010
260 #define ATH9K_TXDESC_VEOL		0x0020
261 #define ATH9K_TXDESC_EXT_ONLY		0x0040
262 #define ATH9K_TXDESC_EXT_AND_CTL	0x0080
263 #define ATH9K_TXDESC_VMF		0x0100
264 #define ATH9K_TXDESC_FRAG_IS_ON 	0x0200
265 #define ATH9K_TXDESC_LOWRXCHAIN		0x0400
266 #define ATH9K_TXDESC_LDPC		0x0800
267 #define ATH9K_TXDESC_CLRDMASK		0x1000
268 
269 #define ATH9K_TXDESC_PAPRD		0x70000
270 #define ATH9K_TXDESC_PAPRD_S		16
271 
272 #define ATH9K_RXDESC_INTREQ		0x0020
273 
274 struct ar5416_desc {
275 	u32 ds_link;
276 	u32 ds_data;
277 	u32 ds_ctl0;
278 	u32 ds_ctl1;
279 	union {
280 		struct {
281 			u32 ctl2;
282 			u32 ctl3;
283 			u32 ctl4;
284 			u32 ctl5;
285 			u32 ctl6;
286 			u32 ctl7;
287 			u32 ctl8;
288 			u32 ctl9;
289 			u32 ctl10;
290 			u32 ctl11;
291 			u32 status0;
292 			u32 status1;
293 			u32 status2;
294 			u32 status3;
295 			u32 status4;
296 			u32 status5;
297 			u32 status6;
298 			u32 status7;
299 			u32 status8;
300 			u32 status9;
301 		} tx;
302 		struct {
303 			u32 status0;
304 			u32 status1;
305 			u32 status2;
306 			u32 status3;
307 			u32 status4;
308 			u32 status5;
309 			u32 status6;
310 			u32 status7;
311 			u32 status8;
312 		} rx;
313 	} u;
314 } __packed __aligned(4);
315 
316 #define AR5416DESC(_ds)         ((struct ar5416_desc *)(_ds))
317 #define AR5416DESC_CONST(_ds)   ((const struct ar5416_desc *)(_ds))
318 
319 #define ds_ctl2     u.tx.ctl2
320 #define ds_ctl3     u.tx.ctl3
321 #define ds_ctl4     u.tx.ctl4
322 #define ds_ctl5     u.tx.ctl5
323 #define ds_ctl6     u.tx.ctl6
324 #define ds_ctl7     u.tx.ctl7
325 #define ds_ctl8     u.tx.ctl8
326 #define ds_ctl9     u.tx.ctl9
327 #define ds_ctl10    u.tx.ctl10
328 #define ds_ctl11    u.tx.ctl11
329 
330 #define ds_txstatus0    u.tx.status0
331 #define ds_txstatus1    u.tx.status1
332 #define ds_txstatus2    u.tx.status2
333 #define ds_txstatus3    u.tx.status3
334 #define ds_txstatus4    u.tx.status4
335 #define ds_txstatus5    u.tx.status5
336 #define ds_txstatus6    u.tx.status6
337 #define ds_txstatus7    u.tx.status7
338 #define ds_txstatus8    u.tx.status8
339 #define ds_txstatus9    u.tx.status9
340 
341 #define ds_rxstatus0    u.rx.status0
342 #define ds_rxstatus1    u.rx.status1
343 #define ds_rxstatus2    u.rx.status2
344 #define ds_rxstatus3    u.rx.status3
345 #define ds_rxstatus4    u.rx.status4
346 #define ds_rxstatus5    u.rx.status5
347 #define ds_rxstatus6    u.rx.status6
348 #define ds_rxstatus7    u.rx.status7
349 #define ds_rxstatus8    u.rx.status8
350 
351 #define AR_FrameLen         0x00000fff
352 #define AR_VirtMoreFrag     0x00001000
353 #define AR_TxCtlRsvd00      0x0000e000
354 #define AR_XmitPower0       0x003f0000
355 #define AR_XmitPower0_S     16
356 #define AR_XmitPower1	    0x3f000000
357 #define AR_XmitPower1_S     24
358 #define AR_XmitPower2	    0x3f000000
359 #define AR_XmitPower2_S     24
360 #define AR_XmitPower3	    0x3f000000
361 #define AR_XmitPower3_S     24
362 #define AR_RTSEnable        0x00400000
363 #define AR_VEOL             0x00800000
364 #define AR_ClrDestMask      0x01000000
365 #define AR_TxCtlRsvd01      0x1e000000
366 #define AR_TxIntrReq        0x20000000
367 #define AR_DestIdxValid     0x40000000
368 #define AR_CTSEnable        0x80000000
369 
370 #define AR_TxMore           0x00001000
371 #define AR_DestIdx          0x000fe000
372 #define AR_DestIdx_S        13
373 #define AR_FrameType        0x00f00000
374 #define AR_FrameType_S      20
375 #define AR_NoAck            0x01000000
376 #define AR_InsertTS         0x02000000
377 #define AR_CorruptFCS       0x04000000
378 #define AR_ExtOnly          0x08000000
379 #define AR_ExtAndCtl        0x10000000
380 #define AR_MoreAggr         0x20000000
381 #define AR_IsAggr           0x40000000
382 
383 #define AR_BurstDur         0x00007fff
384 #define AR_BurstDur_S       0
385 #define AR_DurUpdateEna     0x00008000
386 #define AR_XmitDataTries0   0x000f0000
387 #define AR_XmitDataTries0_S 16
388 #define AR_XmitDataTries1   0x00f00000
389 #define AR_XmitDataTries1_S 20
390 #define AR_XmitDataTries2   0x0f000000
391 #define AR_XmitDataTries2_S 24
392 #define AR_XmitDataTries3   0xf0000000
393 #define AR_XmitDataTries3_S 28
394 
395 #define AR_XmitRate0        0x000000ff
396 #define AR_XmitRate0_S      0
397 #define AR_XmitRate1        0x0000ff00
398 #define AR_XmitRate1_S      8
399 #define AR_XmitRate2        0x00ff0000
400 #define AR_XmitRate2_S      16
401 #define AR_XmitRate3        0xff000000
402 #define AR_XmitRate3_S      24
403 
404 #define AR_PacketDur0       0x00007fff
405 #define AR_PacketDur0_S     0
406 #define AR_RTSCTSQual0      0x00008000
407 #define AR_PacketDur1       0x7fff0000
408 #define AR_PacketDur1_S     16
409 #define AR_RTSCTSQual1      0x80000000
410 
411 #define AR_PacketDur2       0x00007fff
412 #define AR_PacketDur2_S     0
413 #define AR_RTSCTSQual2      0x00008000
414 #define AR_PacketDur3       0x7fff0000
415 #define AR_PacketDur3_S     16
416 #define AR_RTSCTSQual3      0x80000000
417 
418 #define AR_AggrLen          0x0000ffff
419 #define AR_AggrLen_S        0
420 #define AR_TxCtlRsvd60      0x00030000
421 #define AR_PadDelim         0x03fc0000
422 #define AR_PadDelim_S       18
423 #define AR_EncrType         0x0c000000
424 #define AR_EncrType_S       26
425 #define AR_TxCtlRsvd61      0xf0000000
426 #define AR_LDPC             0x80000000
427 
428 #define AR_2040_0           0x00000001
429 #define AR_GI0              0x00000002
430 #define AR_ChainSel0        0x0000001c
431 #define AR_ChainSel0_S      2
432 #define AR_2040_1           0x00000020
433 #define AR_GI1              0x00000040
434 #define AR_ChainSel1        0x00000380
435 #define AR_ChainSel1_S      7
436 #define AR_2040_2           0x00000400
437 #define AR_GI2              0x00000800
438 #define AR_ChainSel2        0x00007000
439 #define AR_ChainSel2_S      12
440 #define AR_2040_3           0x00008000
441 #define AR_GI3              0x00010000
442 #define AR_ChainSel3        0x000e0000
443 #define AR_ChainSel3_S      17
444 #define AR_RTSCTSRate       0x0ff00000
445 #define AR_RTSCTSRate_S     20
446 #define AR_STBC0            0x10000000
447 #define AR_STBC1            0x20000000
448 #define AR_STBC2            0x40000000
449 #define AR_STBC3            0x80000000
450 
451 #define AR_TxRSSIAnt00      0x000000ff
452 #define AR_TxRSSIAnt00_S    0
453 #define AR_TxRSSIAnt01      0x0000ff00
454 #define AR_TxRSSIAnt01_S    8
455 #define AR_TxRSSIAnt02      0x00ff0000
456 #define AR_TxRSSIAnt02_S    16
457 #define AR_TxStatusRsvd00   0x3f000000
458 #define AR_TxBaStatus       0x40000000
459 #define AR_TxStatusRsvd01   0x80000000
460 
461 /*
462  * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
463  * transmitted successfully. If clear, no ACK or BA was received to indicate
464  * successful transmission when we were expecting an ACK or BA.
465  */
466 #define AR_FrmXmitOK            0x00000001
467 #define AR_ExcessiveRetries     0x00000002
468 #define AR_FIFOUnderrun         0x00000004
469 #define AR_Filtered             0x00000008
470 #define AR_RTSFailCnt           0x000000f0
471 #define AR_RTSFailCnt_S         4
472 #define AR_DataFailCnt          0x00000f00
473 #define AR_DataFailCnt_S        8
474 #define AR_VirtRetryCnt         0x0000f000
475 #define AR_VirtRetryCnt_S       12
476 #define AR_TxDelimUnderrun      0x00010000
477 #define AR_TxDataUnderrun       0x00020000
478 #define AR_DescCfgErr           0x00040000
479 #define AR_TxTimerExpired       0x00080000
480 #define AR_TxStatusRsvd10       0xfff00000
481 
482 #define AR_SendTimestamp    ds_txstatus2
483 #define AR_BaBitmapLow      ds_txstatus3
484 #define AR_BaBitmapHigh     ds_txstatus4
485 
486 #define AR_TxRSSIAnt10      0x000000ff
487 #define AR_TxRSSIAnt10_S    0
488 #define AR_TxRSSIAnt11      0x0000ff00
489 #define AR_TxRSSIAnt11_S    8
490 #define AR_TxRSSIAnt12      0x00ff0000
491 #define AR_TxRSSIAnt12_S    16
492 #define AR_TxRSSICombined   0xff000000
493 #define AR_TxRSSICombined_S 24
494 
495 #define AR_TxTid	0xf0000000
496 #define AR_TxTid_S	28
497 
498 #define AR_TxEVM0           ds_txstatus5
499 #define AR_TxEVM1           ds_txstatus6
500 #define AR_TxEVM2           ds_txstatus7
501 
502 #define AR_TxDone           0x00000001
503 #define AR_SeqNum           0x00001ffe
504 #define AR_SeqNum_S         1
505 #define AR_TxStatusRsvd80   0x0001e000
506 #define AR_TxOpExceeded     0x00020000
507 #define AR_TxStatusRsvd81   0x001c0000
508 #define AR_FinalTxIdx       0x00600000
509 #define AR_FinalTxIdx_S     21
510 #define AR_TxStatusRsvd82   0x01800000
511 #define AR_PowerMgmt        0x02000000
512 #define AR_TxStatusRsvd83   0xfc000000
513 
514 #define AR_RxCTLRsvd00  0xffffffff
515 
516 #define AR_RxCtlRsvd00  0x00001000
517 #define AR_RxIntrReq    0x00002000
518 #define AR_RxCtlRsvd01  0xffffc000
519 
520 #define AR_RxRSSIAnt00      0x000000ff
521 #define AR_RxRSSIAnt00_S    0
522 #define AR_RxRSSIAnt01      0x0000ff00
523 #define AR_RxRSSIAnt01_S    8
524 #define AR_RxRSSIAnt02      0x00ff0000
525 #define AR_RxRSSIAnt02_S    16
526 #define AR_RxRate           0xff000000
527 #define AR_RxRate_S         24
528 #define AR_RxStatusRsvd00   0xff000000
529 
530 #define AR_DataLen          0x00000fff
531 #define AR_RxMore           0x00001000
532 #define AR_NumDelim         0x003fc000
533 #define AR_NumDelim_S       14
534 #define AR_RxStatusRsvd10   0xff800000
535 
536 #define AR_RcvTimestamp     ds_rxstatus2
537 
538 #define AR_GI               0x00000001
539 #define AR_2040             0x00000002
540 #define AR_Parallel40       0x00000004
541 #define AR_Parallel40_S     2
542 #define AR_STBC             0x00000008 /* on ar9280 and later */
543 #define AR_RxStatusRsvd30   0x000000f0
544 #define AR_RxAntenna	    0xffffff00
545 #define AR_RxAntenna_S	    8
546 
547 #define AR_RxRSSIAnt10            0x000000ff
548 #define AR_RxRSSIAnt10_S          0
549 #define AR_RxRSSIAnt11            0x0000ff00
550 #define AR_RxRSSIAnt11_S          8
551 #define AR_RxRSSIAnt12            0x00ff0000
552 #define AR_RxRSSIAnt12_S          16
553 #define AR_RxRSSICombined         0xff000000
554 #define AR_RxRSSICombined_S       24
555 
556 #define AR_RxEVM0           ds_rxstatus4
557 #define AR_RxEVM1           ds_rxstatus5
558 #define AR_RxEVM2           ds_rxstatus6
559 
560 #define AR_RxDone           0x00000001
561 #define AR_RxFrameOK        0x00000002
562 #define AR_CRCErr           0x00000004
563 #define AR_DecryptCRCErr    0x00000008
564 #define AR_PHYErr           0x00000010
565 #define AR_MichaelErr       0x00000020
566 #define AR_PreDelimCRCErr   0x00000040
567 #define AR_RxStatusRsvd70   0x00000080
568 #define AR_RxKeyIdxValid    0x00000100
569 #define AR_KeyIdx           0x0000fe00
570 #define AR_KeyIdx_S         9
571 #define AR_PHYErrCode       0x0000ff00
572 #define AR_PHYErrCode_S     8
573 #define AR_RxMoreAggr       0x00010000
574 #define AR_RxAggr           0x00020000
575 #define AR_PostDelimCRCErr  0x00040000
576 #define AR_RxStatusRsvd71   0x3ff80000
577 #define AR_RxFirstAggr      0x20000000
578 #define AR_DecryptBusyErr   0x40000000
579 #define AR_KeyMiss          0x80000000
580 
581 enum ath9k_tx_queue {
582 	ATH9K_TX_QUEUE_INACTIVE = 0,
583 	ATH9K_TX_QUEUE_DATA,
584 	ATH9K_TX_QUEUE_BEACON,
585 	ATH9K_TX_QUEUE_CAB,
586 	ATH9K_TX_QUEUE_UAPSD,
587 	ATH9K_TX_QUEUE_PSPOLL
588 };
589 
590 #define	ATH9K_NUM_TX_QUEUES 10
591 
592 /* Used as a queue subtype instead of a WMM AC */
593 #define ATH9K_WME_UPSD	4
594 
595 enum ath9k_tx_queue_flags {
596 	TXQ_FLAG_TXINT_ENABLE = 0x0001,
597 	TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
598 	TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
599 	TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
600 	TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
601 	TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
602 	TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
603 	TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
604 };
605 
606 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
607 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
608 
609 #define ATH9K_DECOMP_MASK_SIZE     128
610 
611 enum ath9k_pkt_type {
612 	ATH9K_PKT_TYPE_NORMAL = 0,
613 	ATH9K_PKT_TYPE_ATIM,
614 	ATH9K_PKT_TYPE_PSPOLL,
615 	ATH9K_PKT_TYPE_BEACON,
616 	ATH9K_PKT_TYPE_PROBE_RESP,
617 	ATH9K_PKT_TYPE_CHIRP,
618 	ATH9K_PKT_TYPE_GRP_POLL,
619 };
620 
621 struct ath9k_tx_queue_info {
622 	u32 tqi_ver;
623 	enum ath9k_tx_queue tqi_type;
624 	int tqi_subtype;
625 	enum ath9k_tx_queue_flags tqi_qflags;
626 	u32 tqi_priority;
627 	u32 tqi_aifs;
628 	u32 tqi_cwmin;
629 	u32 tqi_cwmax;
630 	u16 tqi_shretry;
631 	u16 tqi_lgretry;
632 	u32 tqi_cbrPeriod;
633 	u32 tqi_cbrOverflowLimit;
634 	u32 tqi_burstTime;
635 	u32 tqi_readyTime;
636 	u32 tqi_physCompBuf;
637 	u32 tqi_intFlags;
638 };
639 
640 enum ath9k_rx_filter {
641 	ATH9K_RX_FILTER_UCAST = 0x00000001,
642 	ATH9K_RX_FILTER_MCAST = 0x00000002,
643 	ATH9K_RX_FILTER_BCAST = 0x00000004,
644 	ATH9K_RX_FILTER_CONTROL = 0x00000008,
645 	ATH9K_RX_FILTER_BEACON = 0x00000010,
646 	ATH9K_RX_FILTER_PROM = 0x00000020,
647 	ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
648 	ATH9K_RX_FILTER_PHYERR = 0x00000100,
649 	ATH9K_RX_FILTER_MYBEACON = 0x00000200,
650 	ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
651 	ATH9K_RX_FILTER_COMP_BA = 0x00000800,
652 	ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000,
653 	ATH9K_RX_FILTER_PSPOLL = 0x00004000,
654 	ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
655 	ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
656 	ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000,
657 	ATH9K_RX_FILTER_4ADDRESS = 0x00100000,
658 };
659 
660 #define ATH9K_RATESERIES_RTS_CTS  0x0001
661 #define ATH9K_RATESERIES_2040     0x0002
662 #define ATH9K_RATESERIES_HALFGI   0x0004
663 #define ATH9K_RATESERIES_STBC     0x0008
664 
665 struct ath9k_11n_rate_series {
666 	u32 Tries;
667 	u32 Rate;
668 	u32 PktDuration;
669 	u32 ChSel;
670 	u32 RateFlags;
671 };
672 
673 enum aggr_type {
674 	AGGR_BUF_NONE,
675 	AGGR_BUF_FIRST,
676 	AGGR_BUF_MIDDLE,
677 	AGGR_BUF_LAST,
678 };
679 
680 enum ath9k_key_type {
681 	ATH9K_KEY_TYPE_CLEAR,
682 	ATH9K_KEY_TYPE_WEP,
683 	ATH9K_KEY_TYPE_AES,
684 	ATH9K_KEY_TYPE_TKIP,
685 };
686 
687 struct ath_tx_info {
688 	u8 qcu;
689 
690 	bool is_first;
691 	bool is_last;
692 
693 	enum aggr_type aggr;
694 	u8 ndelim;
695 	u16 aggr_len;
696 
697 	dma_addr_t link;
698 	int pkt_len;
699 	u32 flags;
700 
701 	dma_addr_t buf_addr[4];
702 	int buf_len[4];
703 
704 	struct ath9k_11n_rate_series rates[4];
705 	u8 rtscts_rate;
706 	bool dur_update;
707 
708 	enum ath9k_pkt_type type;
709 	enum ath9k_key_type keytype;
710 	u8 keyix;
711 	u8 txpower[4];
712 };
713 
714 struct ath_hw;
715 struct ath9k_channel;
716 enum ath9k_int;
717 
718 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
719 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
720 void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
721 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
722 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
723 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
724 void ath9k_hw_abort_tx_dma(struct ath_hw *ah);
725 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
726 			    const struct ath9k_tx_queue_info *qinfo);
727 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
728 			    struct ath9k_tx_queue_info *qinfo);
729 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
730 			  const struct ath9k_tx_queue_info *qinfo);
731 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
732 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
733 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
734 			struct ath_rx_status *rs);
735 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
736 			  u32 size, u32 flags);
737 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
738 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
739 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
740 void ath9k_hw_abortpcurecv(struct ath_hw *ah);
741 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset);
742 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
743 void ath9k_hw_set_tx_filter(struct ath_hw *ah, u8 destidx, bool set);
744 
745 /* Interrupt Handling */
746 bool ath9k_hw_intrpend(struct ath_hw *ah);
747 void ath9k_hw_set_interrupts(struct ath_hw *ah);
748 void ath9k_hw_enable_interrupts(struct ath_hw *ah);
749 void ath9k_hw_disable_interrupts(struct ath_hw *ah);
750 void ath9k_hw_kill_interrupts(struct ath_hw *ah);
751 void ath9k_hw_resume_interrupts(struct ath_hw *ah);
752 
753 void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
754 
755 #endif /* MAC_H */
756