Searched refs:APMU_CCIC1 (Results 1 – 2 of 2) sorted by relevance
| /linux-5.19.10/drivers/clk/mmp/ |
| D | clk-mmp2.c | 52 #define APMU_CCIC1 0xf4 macro
433 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); in mmp2_clk_init()
437 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, in mmp2_clk_init()
442 apmu_base + APMU_CCIC1, 0x1b, &clk_lock); in mmp2_clk_init()
446 apmu_base + APMU_CCIC1, 0x24, &clk_lock); in mmp2_clk_init()
450 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, in mmp2_clk_init()
455 apmu_base + APMU_CCIC1, 0x300, &clk_lock); in mmp2_clk_init()
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| D | clk-of-mmp2.c | 63 #define APMU_CCIC1 0xf4 macro
354 {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
379 …{MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0…
380 …{MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24…
381 …{MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, …
414 ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1; in mmp2_axi_periph_clk_init()
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