Searched refs:APBC_PWM3 (Results 1 – 6 of 6) sorted by relevance
| /linux-5.19.10/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 34 #define APBC_PWM3 0x18 macro
151 …{PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_…
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| D | clk-pxa910.c | 32 #define APBC_PWM3 0x18 macro
202 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in pxa910_clk_init()
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| D | clk-of-pxa910.c | 34 #define APBC_PWM3 0x18 macro
149 …{PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_…
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| D | clk-pxa168.c | 32 #define APBC_PWM3 0x18 macro
197 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 39 #define APBC_PWM3 0x48 macro
242 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in mmp2_clk_init()
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| D | clk-of-mmp2.c | 45 #define APBC_PWM3 0x48 macro
264 …{MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lo…
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