1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * AD9832 SPI DDS driver
4  *
5  * Copyright 2011 Analog Devices Inc.
6  */
7 
8 #include <asm/div64.h>
9 
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <linux/spi/spi.h>
18 #include <linux/sysfs.h>
19 
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 
23 #include "ad9832.h"
24 
25 #include "dds.h"
26 
27 /* Registers */
28 
29 #define AD9832_FREQ0LL		0x0
30 #define AD9832_FREQ0HL		0x1
31 #define AD9832_FREQ0LM		0x2
32 #define AD9832_FREQ0HM		0x3
33 #define AD9832_FREQ1LL		0x4
34 #define AD9832_FREQ1HL		0x5
35 #define AD9832_FREQ1LM		0x6
36 #define AD9832_FREQ1HM		0x7
37 #define AD9832_PHASE0L		0x8
38 #define AD9832_PHASE0H		0x9
39 #define AD9832_PHASE1L		0xA
40 #define AD9832_PHASE1H		0xB
41 #define AD9832_PHASE2L		0xC
42 #define AD9832_PHASE2H		0xD
43 #define AD9832_PHASE3L		0xE
44 #define AD9832_PHASE3H		0xF
45 
46 #define AD9832_PHASE_SYM	0x10
47 #define AD9832_FREQ_SYM		0x11
48 #define AD9832_PINCTRL_EN	0x12
49 #define AD9832_OUTPUT_EN	0x13
50 
51 /* Command Control Bits */
52 
53 #define AD9832_CMD_PHA8BITSW	0x1
54 #define AD9832_CMD_PHA16BITSW	0x0
55 #define AD9832_CMD_FRE8BITSW	0x3
56 #define AD9832_CMD_FRE16BITSW	0x2
57 #define AD9832_CMD_FPSELECT	0x6
58 #define AD9832_CMD_SYNCSELSRC	0x8
59 #define AD9832_CMD_SLEEPRESCLR	0xC
60 
61 #define AD9832_FREQ		BIT(11)
62 #define AD9832_PHASE(x)		(((x) & 3) << 9)
63 #define AD9832_SYNC		BIT(13)
64 #define AD9832_SELSRC		BIT(12)
65 #define AD9832_SLEEP		BIT(13)
66 #define AD9832_RESET		BIT(12)
67 #define AD9832_CLR		BIT(11)
68 #define CMD_SHIFT		12
69 #define ADD_SHIFT		8
70 #define AD9832_FREQ_BITS	32
71 #define AD9832_PHASE_BITS	12
72 #define RES_MASK(bits)		((1 << (bits)) - 1)
73 
74 /**
75  * struct ad9832_state - driver instance specific data
76  * @spi:		spi_device
77  * @avdd:		supply regulator for the analog section
78  * @dvdd:		supply regulator for the digital section
79  * @mclk:		external master clock
80  * @ctrl_fp:		cached frequency/phase control word
81  * @ctrl_ss:		cached sync/selsrc control word
82  * @ctrl_src:		cached sleep/reset/clr word
83  * @xfer:		default spi transfer
84  * @msg:		default spi message
85  * @freq_xfer:		tuning word spi transfer
86  * @freq_msg:		tuning word spi message
87  * @phase_xfer:		tuning word spi transfer
88  * @phase_msg:		tuning word spi message
89  * @lock:		protect sensor state
90  * @data:		spi transmit buffer
91  * @phase_data:		tuning word spi transmit buffer
92  * @freq_data:		tuning word spi transmit buffer
93  */
94 
95 struct ad9832_state {
96 	struct spi_device		*spi;
97 	struct regulator		*avdd;
98 	struct regulator		*dvdd;
99 	struct clk			*mclk;
100 	unsigned short			ctrl_fp;
101 	unsigned short			ctrl_ss;
102 	unsigned short			ctrl_src;
103 	struct spi_transfer		xfer;
104 	struct spi_message		msg;
105 	struct spi_transfer		freq_xfer[4];
106 	struct spi_message		freq_msg;
107 	struct spi_transfer		phase_xfer[2];
108 	struct spi_message		phase_msg;
109 	struct mutex			lock;	/* protect sensor state */
110 	/*
111 	 * DMA (thus cache coherency maintenance) requires the
112 	 * transfer buffers to live in their own cache lines.
113 	 */
114 	union {
115 		__be16			freq_data[4]____cacheline_aligned;
116 		__be16			phase_data[2];
117 		__be16			data;
118 	};
119 };
120 
ad9832_calc_freqreg(unsigned long mclk,unsigned long fout)121 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
122 {
123 	unsigned long long freqreg = (u64)fout *
124 				     (u64)((u64)1L << AD9832_FREQ_BITS);
125 	do_div(freqreg, mclk);
126 	return freqreg;
127 }
128 
ad9832_write_frequency(struct ad9832_state * st,unsigned int addr,unsigned long fout)129 static int ad9832_write_frequency(struct ad9832_state *st,
130 				  unsigned int addr, unsigned long fout)
131 {
132 	unsigned long regval;
133 
134 	if (fout > (clk_get_rate(st->mclk) / 2))
135 		return -EINVAL;
136 
137 	regval = ad9832_calc_freqreg(clk_get_rate(st->mclk), fout);
138 
139 	st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
140 					(addr << ADD_SHIFT) |
141 					((regval >> 24) & 0xFF));
142 	st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
143 					((addr - 1) << ADD_SHIFT) |
144 					((regval >> 16) & 0xFF));
145 	st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
146 					((addr - 2) << ADD_SHIFT) |
147 					((regval >> 8) & 0xFF));
148 	st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
149 					((addr - 3) << ADD_SHIFT) |
150 					((regval >> 0) & 0xFF));
151 
152 	return spi_sync(st->spi, &st->freq_msg);
153 }
154 
ad9832_write_phase(struct ad9832_state * st,unsigned long addr,unsigned long phase)155 static int ad9832_write_phase(struct ad9832_state *st,
156 			      unsigned long addr, unsigned long phase)
157 {
158 	if (phase > BIT(AD9832_PHASE_BITS))
159 		return -EINVAL;
160 
161 	st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
162 					(addr << ADD_SHIFT) |
163 					((phase >> 8) & 0xFF));
164 	st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
165 					((addr - 1) << ADD_SHIFT) |
166 					(phase & 0xFF));
167 
168 	return spi_sync(st->spi, &st->phase_msg);
169 }
170 
ad9832_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)171 static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
172 			    const char *buf, size_t len)
173 {
174 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
175 	struct ad9832_state *st = iio_priv(indio_dev);
176 	struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
177 	int ret;
178 	unsigned long val;
179 
180 	ret = kstrtoul(buf, 10, &val);
181 	if (ret)
182 		goto error_ret;
183 
184 	mutex_lock(&st->lock);
185 	switch ((u32)this_attr->address) {
186 	case AD9832_FREQ0HM:
187 	case AD9832_FREQ1HM:
188 		ret = ad9832_write_frequency(st, this_attr->address, val);
189 		break;
190 	case AD9832_PHASE0H:
191 	case AD9832_PHASE1H:
192 	case AD9832_PHASE2H:
193 	case AD9832_PHASE3H:
194 		ret = ad9832_write_phase(st, this_attr->address, val);
195 		break;
196 	case AD9832_PINCTRL_EN:
197 		if (val)
198 			st->ctrl_ss &= ~AD9832_SELSRC;
199 		else
200 			st->ctrl_ss |= AD9832_SELSRC;
201 		st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
202 					st->ctrl_ss);
203 		ret = spi_sync(st->spi, &st->msg);
204 		break;
205 	case AD9832_FREQ_SYM:
206 		if (val == 1) {
207 			st->ctrl_fp |= AD9832_FREQ;
208 		} else if (val == 0) {
209 			st->ctrl_fp &= ~AD9832_FREQ;
210 		} else {
211 			ret = -EINVAL;
212 			break;
213 		}
214 		st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
215 					st->ctrl_fp);
216 		ret = spi_sync(st->spi, &st->msg);
217 		break;
218 	case AD9832_PHASE_SYM:
219 		if (val > 3) {
220 			ret = -EINVAL;
221 			break;
222 		}
223 
224 		st->ctrl_fp &= ~AD9832_PHASE(3);
225 		st->ctrl_fp |= AD9832_PHASE(val);
226 
227 		st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
228 					st->ctrl_fp);
229 		ret = spi_sync(st->spi, &st->msg);
230 		break;
231 	case AD9832_OUTPUT_EN:
232 		if (val)
233 			st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
234 					AD9832_CLR);
235 		else
236 			st->ctrl_src |= AD9832_RESET;
237 
238 		st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
239 					st->ctrl_src);
240 		ret = spi_sync(st->spi, &st->msg);
241 		break;
242 	default:
243 		ret = -ENODEV;
244 	}
245 	mutex_unlock(&st->lock);
246 
247 error_ret:
248 	return ret ? ret : len;
249 }
250 
251 /*
252  * see dds.h for further information
253  */
254 
255 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9832_write, AD9832_FREQ0HM);
256 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9832_write, AD9832_FREQ1HM);
257 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9832_write, AD9832_FREQ_SYM);
258 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
259 
260 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9832_write, AD9832_PHASE0H);
261 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9832_write, AD9832_PHASE1H);
262 static IIO_DEV_ATTR_PHASE(0, 2, 0200, NULL, ad9832_write, AD9832_PHASE2H);
263 static IIO_DEV_ATTR_PHASE(0, 3, 0200, NULL, ad9832_write, AD9832_PHASE3H);
264 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL,
265 				ad9832_write, AD9832_PHASE_SYM);
266 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
267 
268 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
269 				ad9832_write, AD9832_PINCTRL_EN);
270 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL,
271 				ad9832_write, AD9832_OUTPUT_EN);
272 
273 static struct attribute *ad9832_attributes[] = {
274 	&iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
275 	&iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
276 	&iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
277 	&iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
278 	&iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
279 	&iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
280 	&iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
281 	&iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
282 	&iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
283 	&iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
284 	&iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
285 	&iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
286 	NULL,
287 };
288 
289 static const struct attribute_group ad9832_attribute_group = {
290 	.attrs = ad9832_attributes,
291 };
292 
293 static const struct iio_info ad9832_info = {
294 	.attrs = &ad9832_attribute_group,
295 };
296 
ad9832_reg_disable(void * reg)297 static void ad9832_reg_disable(void *reg)
298 {
299 	regulator_disable(reg);
300 }
301 
ad9832_clk_disable(void * clk)302 static void ad9832_clk_disable(void *clk)
303 {
304 	clk_disable_unprepare(clk);
305 }
306 
ad9832_probe(struct spi_device * spi)307 static int ad9832_probe(struct spi_device *spi)
308 {
309 	struct ad9832_platform_data *pdata = dev_get_platdata(&spi->dev);
310 	struct iio_dev *indio_dev;
311 	struct ad9832_state *st;
312 	int ret;
313 
314 	if (!pdata) {
315 		dev_dbg(&spi->dev, "no platform data?\n");
316 		return -ENODEV;
317 	}
318 
319 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
320 	if (!indio_dev)
321 		return -ENOMEM;
322 
323 	st = iio_priv(indio_dev);
324 
325 	st->avdd = devm_regulator_get(&spi->dev, "avdd");
326 	if (IS_ERR(st->avdd))
327 		return PTR_ERR(st->avdd);
328 
329 	ret = regulator_enable(st->avdd);
330 	if (ret) {
331 		dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
332 		return ret;
333 	}
334 
335 	ret = devm_add_action_or_reset(&spi->dev, ad9832_reg_disable, st->avdd);
336 	if (ret)
337 		return ret;
338 
339 	st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
340 	if (IS_ERR(st->dvdd))
341 		return PTR_ERR(st->dvdd);
342 
343 	ret = regulator_enable(st->dvdd);
344 	if (ret) {
345 		dev_err(&spi->dev, "Failed to enable specified DVDD supply\n");
346 		return ret;
347 	}
348 
349 	ret = devm_add_action_or_reset(&spi->dev, ad9832_reg_disable, st->dvdd);
350 	if (ret)
351 		return ret;
352 
353 	st->mclk = devm_clk_get(&spi->dev, "mclk");
354 	if (IS_ERR(st->mclk))
355 		return PTR_ERR(st->mclk);
356 
357 	ret = clk_prepare_enable(st->mclk);
358 	if (ret < 0)
359 		return ret;
360 
361 	ret = devm_add_action_or_reset(&spi->dev, ad9832_clk_disable, st->mclk);
362 	if (ret)
363 		return ret;
364 
365 	st->spi = spi;
366 	mutex_init(&st->lock);
367 
368 	indio_dev->name = spi_get_device_id(spi)->name;
369 	indio_dev->info = &ad9832_info;
370 	indio_dev->modes = INDIO_DIRECT_MODE;
371 
372 	/* Setup default messages */
373 
374 	st->xfer.tx_buf = &st->data;
375 	st->xfer.len = 2;
376 
377 	spi_message_init(&st->msg);
378 	spi_message_add_tail(&st->xfer, &st->msg);
379 
380 	st->freq_xfer[0].tx_buf = &st->freq_data[0];
381 	st->freq_xfer[0].len = 2;
382 	st->freq_xfer[0].cs_change = 1;
383 	st->freq_xfer[1].tx_buf = &st->freq_data[1];
384 	st->freq_xfer[1].len = 2;
385 	st->freq_xfer[1].cs_change = 1;
386 	st->freq_xfer[2].tx_buf = &st->freq_data[2];
387 	st->freq_xfer[2].len = 2;
388 	st->freq_xfer[2].cs_change = 1;
389 	st->freq_xfer[3].tx_buf = &st->freq_data[3];
390 	st->freq_xfer[3].len = 2;
391 
392 	spi_message_init(&st->freq_msg);
393 	spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
394 	spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
395 	spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
396 	spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
397 
398 	st->phase_xfer[0].tx_buf = &st->phase_data[0];
399 	st->phase_xfer[0].len = 2;
400 	st->phase_xfer[0].cs_change = 1;
401 	st->phase_xfer[1].tx_buf = &st->phase_data[1];
402 	st->phase_xfer[1].len = 2;
403 
404 	spi_message_init(&st->phase_msg);
405 	spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
406 	spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
407 
408 	st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
409 	st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
410 					st->ctrl_src);
411 	ret = spi_sync(st->spi, &st->msg);
412 	if (ret) {
413 		dev_err(&spi->dev, "device init failed\n");
414 		return ret;
415 	}
416 
417 	ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
418 	if (ret)
419 		return ret;
420 
421 	ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
422 	if (ret)
423 		return ret;
424 
425 	ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
426 	if (ret)
427 		return ret;
428 
429 	ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
430 	if (ret)
431 		return ret;
432 
433 	ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
434 	if (ret)
435 		return ret;
436 
437 	ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
438 	if (ret)
439 		return ret;
440 
441 	return devm_iio_device_register(&spi->dev, indio_dev);
442 }
443 
444 static const struct spi_device_id ad9832_id[] = {
445 	{"ad9832", 0},
446 	{"ad9835", 0},
447 	{}
448 };
449 MODULE_DEVICE_TABLE(spi, ad9832_id);
450 
451 static struct spi_driver ad9832_driver = {
452 	.driver = {
453 		.name	= "ad9832",
454 	},
455 	.probe		= ad9832_probe,
456 	.id_table	= ad9832_id,
457 };
458 module_spi_driver(ad9832_driver);
459 
460 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
461 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
462 MODULE_LICENSE("GPL v2");
463