1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 Huawei Ltd.
4 * Author: Jiang Liu <liuj97@gmail.com>
5 *
6 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7 */
8 #ifndef __ASM_INSN_H
9 #define __ASM_INSN_H
10 #include <linux/build_bug.h>
11 #include <linux/types.h>
12
13 #include <asm/insn-def.h>
14
15 #ifndef __ASSEMBLY__
16 /*
17 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
18 * Section C3.1 "A64 instruction index by encoding":
19 * AArch64 main encoding table
20 * Bit position
21 * 28 27 26 25 Encoding Group
22 * 0 0 - - Unallocated
23 * 1 0 0 - Data processing, immediate
24 * 1 0 1 - Branch, exception generation and system instructions
25 * - 1 - 0 Loads and stores
26 * - 1 0 1 Data processing - register
27 * 0 1 1 1 Data processing - SIMD and floating point
28 * 1 1 1 1 Data processing - SIMD and floating point
29 * "-" means "don't care"
30 */
31 enum aarch64_insn_encoding_class {
32 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
33 AARCH64_INSN_CLS_SVE, /* SVE instructions */
34 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
35 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
36 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
37 AARCH64_INSN_CLS_LDST, /* Loads and stores */
38 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
39 * system instructions */
40 };
41
42 enum aarch64_insn_hint_cr_op {
43 AARCH64_INSN_HINT_NOP = 0x0 << 5,
44 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
45 AARCH64_INSN_HINT_WFE = 0x2 << 5,
46 AARCH64_INSN_HINT_WFI = 0x3 << 5,
47 AARCH64_INSN_HINT_SEV = 0x4 << 5,
48 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
49
50 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
51 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
52 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
53 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
54 AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
55 AARCH64_INSN_HINT_PACIAZ = 0x18 << 5,
56 AARCH64_INSN_HINT_PACIASP = 0x19 << 5,
57 AARCH64_INSN_HINT_PACIBZ = 0x1A << 5,
58 AARCH64_INSN_HINT_PACIBSP = 0x1B << 5,
59 AARCH64_INSN_HINT_AUTIAZ = 0x1C << 5,
60 AARCH64_INSN_HINT_AUTIASP = 0x1D << 5,
61 AARCH64_INSN_HINT_AUTIBZ = 0x1E << 5,
62 AARCH64_INSN_HINT_AUTIBSP = 0x1F << 5,
63
64 AARCH64_INSN_HINT_ESB = 0x10 << 5,
65 AARCH64_INSN_HINT_PSB = 0x11 << 5,
66 AARCH64_INSN_HINT_TSB = 0x12 << 5,
67 AARCH64_INSN_HINT_CSDB = 0x14 << 5,
68 AARCH64_INSN_HINT_CLEARBHB = 0x16 << 5,
69
70 AARCH64_INSN_HINT_BTI = 0x20 << 5,
71 AARCH64_INSN_HINT_BTIC = 0x22 << 5,
72 AARCH64_INSN_HINT_BTIJ = 0x24 << 5,
73 AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
74 };
75
76 enum aarch64_insn_imm_type {
77 AARCH64_INSN_IMM_ADR,
78 AARCH64_INSN_IMM_26,
79 AARCH64_INSN_IMM_19,
80 AARCH64_INSN_IMM_16,
81 AARCH64_INSN_IMM_14,
82 AARCH64_INSN_IMM_12,
83 AARCH64_INSN_IMM_9,
84 AARCH64_INSN_IMM_7,
85 AARCH64_INSN_IMM_6,
86 AARCH64_INSN_IMM_S,
87 AARCH64_INSN_IMM_R,
88 AARCH64_INSN_IMM_N,
89 AARCH64_INSN_IMM_MAX
90 };
91
92 enum aarch64_insn_register_type {
93 AARCH64_INSN_REGTYPE_RT,
94 AARCH64_INSN_REGTYPE_RN,
95 AARCH64_INSN_REGTYPE_RT2,
96 AARCH64_INSN_REGTYPE_RM,
97 AARCH64_INSN_REGTYPE_RD,
98 AARCH64_INSN_REGTYPE_RA,
99 AARCH64_INSN_REGTYPE_RS,
100 };
101
102 enum aarch64_insn_register {
103 AARCH64_INSN_REG_0 = 0,
104 AARCH64_INSN_REG_1 = 1,
105 AARCH64_INSN_REG_2 = 2,
106 AARCH64_INSN_REG_3 = 3,
107 AARCH64_INSN_REG_4 = 4,
108 AARCH64_INSN_REG_5 = 5,
109 AARCH64_INSN_REG_6 = 6,
110 AARCH64_INSN_REG_7 = 7,
111 AARCH64_INSN_REG_8 = 8,
112 AARCH64_INSN_REG_9 = 9,
113 AARCH64_INSN_REG_10 = 10,
114 AARCH64_INSN_REG_11 = 11,
115 AARCH64_INSN_REG_12 = 12,
116 AARCH64_INSN_REG_13 = 13,
117 AARCH64_INSN_REG_14 = 14,
118 AARCH64_INSN_REG_15 = 15,
119 AARCH64_INSN_REG_16 = 16,
120 AARCH64_INSN_REG_17 = 17,
121 AARCH64_INSN_REG_18 = 18,
122 AARCH64_INSN_REG_19 = 19,
123 AARCH64_INSN_REG_20 = 20,
124 AARCH64_INSN_REG_21 = 21,
125 AARCH64_INSN_REG_22 = 22,
126 AARCH64_INSN_REG_23 = 23,
127 AARCH64_INSN_REG_24 = 24,
128 AARCH64_INSN_REG_25 = 25,
129 AARCH64_INSN_REG_26 = 26,
130 AARCH64_INSN_REG_27 = 27,
131 AARCH64_INSN_REG_28 = 28,
132 AARCH64_INSN_REG_29 = 29,
133 AARCH64_INSN_REG_FP = 29, /* Frame pointer */
134 AARCH64_INSN_REG_30 = 30,
135 AARCH64_INSN_REG_LR = 30, /* Link register */
136 AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
137 AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
138 };
139
140 enum aarch64_insn_special_register {
141 AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200,
142 AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201,
143 AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208,
144 AARCH64_INSN_SPCLREG_SPSEL = 0xC210,
145 AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212,
146 AARCH64_INSN_SPCLREG_DAIF = 0xDA11,
147 AARCH64_INSN_SPCLREG_NZCV = 0xDA10,
148 AARCH64_INSN_SPCLREG_FPCR = 0xDA20,
149 AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28,
150 AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29,
151 AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200,
152 AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201,
153 AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208,
154 AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218,
155 AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219,
156 AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A,
157 AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B,
158 AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200,
159 AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201,
160 AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210
161 };
162
163 enum aarch64_insn_variant {
164 AARCH64_INSN_VARIANT_32BIT,
165 AARCH64_INSN_VARIANT_64BIT
166 };
167
168 enum aarch64_insn_condition {
169 AARCH64_INSN_COND_EQ = 0x0, /* == */
170 AARCH64_INSN_COND_NE = 0x1, /* != */
171 AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
172 AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
173 AARCH64_INSN_COND_MI = 0x4, /* < 0 */
174 AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
175 AARCH64_INSN_COND_VS = 0x6, /* overflow */
176 AARCH64_INSN_COND_VC = 0x7, /* no overflow */
177 AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
178 AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
179 AARCH64_INSN_COND_GE = 0xa, /* signed >= */
180 AARCH64_INSN_COND_LT = 0xb, /* signed < */
181 AARCH64_INSN_COND_GT = 0xc, /* signed > */
182 AARCH64_INSN_COND_LE = 0xd, /* signed <= */
183 AARCH64_INSN_COND_AL = 0xe, /* always */
184 };
185
186 enum aarch64_insn_branch_type {
187 AARCH64_INSN_BRANCH_NOLINK,
188 AARCH64_INSN_BRANCH_LINK,
189 AARCH64_INSN_BRANCH_RETURN,
190 AARCH64_INSN_BRANCH_COMP_ZERO,
191 AARCH64_INSN_BRANCH_COMP_NONZERO,
192 };
193
194 enum aarch64_insn_size_type {
195 AARCH64_INSN_SIZE_8,
196 AARCH64_INSN_SIZE_16,
197 AARCH64_INSN_SIZE_32,
198 AARCH64_INSN_SIZE_64,
199 };
200
201 enum aarch64_insn_ldst_type {
202 AARCH64_INSN_LDST_LOAD_REG_OFFSET,
203 AARCH64_INSN_LDST_STORE_REG_OFFSET,
204 AARCH64_INSN_LDST_LOAD_IMM_OFFSET,
205 AARCH64_INSN_LDST_STORE_IMM_OFFSET,
206 AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
207 AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
208 AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
209 AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
210 AARCH64_INSN_LDST_LOAD_EX,
211 AARCH64_INSN_LDST_LOAD_ACQ_EX,
212 AARCH64_INSN_LDST_STORE_EX,
213 AARCH64_INSN_LDST_STORE_REL_EX,
214 };
215
216 enum aarch64_insn_adsb_type {
217 AARCH64_INSN_ADSB_ADD,
218 AARCH64_INSN_ADSB_SUB,
219 AARCH64_INSN_ADSB_ADD_SETFLAGS,
220 AARCH64_INSN_ADSB_SUB_SETFLAGS
221 };
222
223 enum aarch64_insn_movewide_type {
224 AARCH64_INSN_MOVEWIDE_ZERO,
225 AARCH64_INSN_MOVEWIDE_KEEP,
226 AARCH64_INSN_MOVEWIDE_INVERSE
227 };
228
229 enum aarch64_insn_bitfield_type {
230 AARCH64_INSN_BITFIELD_MOVE,
231 AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
232 AARCH64_INSN_BITFIELD_MOVE_SIGNED
233 };
234
235 enum aarch64_insn_data1_type {
236 AARCH64_INSN_DATA1_REVERSE_16,
237 AARCH64_INSN_DATA1_REVERSE_32,
238 AARCH64_INSN_DATA1_REVERSE_64,
239 };
240
241 enum aarch64_insn_data2_type {
242 AARCH64_INSN_DATA2_UDIV,
243 AARCH64_INSN_DATA2_SDIV,
244 AARCH64_INSN_DATA2_LSLV,
245 AARCH64_INSN_DATA2_LSRV,
246 AARCH64_INSN_DATA2_ASRV,
247 AARCH64_INSN_DATA2_RORV,
248 };
249
250 enum aarch64_insn_data3_type {
251 AARCH64_INSN_DATA3_MADD,
252 AARCH64_INSN_DATA3_MSUB,
253 };
254
255 enum aarch64_insn_logic_type {
256 AARCH64_INSN_LOGIC_AND,
257 AARCH64_INSN_LOGIC_BIC,
258 AARCH64_INSN_LOGIC_ORR,
259 AARCH64_INSN_LOGIC_ORN,
260 AARCH64_INSN_LOGIC_EOR,
261 AARCH64_INSN_LOGIC_EON,
262 AARCH64_INSN_LOGIC_AND_SETFLAGS,
263 AARCH64_INSN_LOGIC_BIC_SETFLAGS
264 };
265
266 enum aarch64_insn_prfm_type {
267 AARCH64_INSN_PRFM_TYPE_PLD,
268 AARCH64_INSN_PRFM_TYPE_PLI,
269 AARCH64_INSN_PRFM_TYPE_PST,
270 };
271
272 enum aarch64_insn_prfm_target {
273 AARCH64_INSN_PRFM_TARGET_L1,
274 AARCH64_INSN_PRFM_TARGET_L2,
275 AARCH64_INSN_PRFM_TARGET_L3,
276 };
277
278 enum aarch64_insn_prfm_policy {
279 AARCH64_INSN_PRFM_POLICY_KEEP,
280 AARCH64_INSN_PRFM_POLICY_STRM,
281 };
282
283 enum aarch64_insn_adr_type {
284 AARCH64_INSN_ADR_TYPE_ADRP,
285 AARCH64_INSN_ADR_TYPE_ADR,
286 };
287
288 enum aarch64_insn_mem_atomic_op {
289 AARCH64_INSN_MEM_ATOMIC_ADD,
290 AARCH64_INSN_MEM_ATOMIC_CLR,
291 AARCH64_INSN_MEM_ATOMIC_EOR,
292 AARCH64_INSN_MEM_ATOMIC_SET,
293 AARCH64_INSN_MEM_ATOMIC_SWP,
294 };
295
296 enum aarch64_insn_mem_order_type {
297 AARCH64_INSN_MEM_ORDER_NONE,
298 AARCH64_INSN_MEM_ORDER_ACQ,
299 AARCH64_INSN_MEM_ORDER_REL,
300 AARCH64_INSN_MEM_ORDER_ACQREL,
301 };
302
303 enum aarch64_insn_mb_type {
304 AARCH64_INSN_MB_SY,
305 AARCH64_INSN_MB_ST,
306 AARCH64_INSN_MB_LD,
307 AARCH64_INSN_MB_ISH,
308 AARCH64_INSN_MB_ISHST,
309 AARCH64_INSN_MB_ISHLD,
310 AARCH64_INSN_MB_NSH,
311 AARCH64_INSN_MB_NSHST,
312 AARCH64_INSN_MB_NSHLD,
313 AARCH64_INSN_MB_OSH,
314 AARCH64_INSN_MB_OSHST,
315 AARCH64_INSN_MB_OSHLD,
316 };
317
318 #define __AARCH64_INSN_FUNCS(abbr, mask, val) \
319 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
320 { \
321 BUILD_BUG_ON(~(mask) & (val)); \
322 return (code & (mask)) == (val); \
323 } \
324 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
325 { \
326 return (val); \
327 }
328
329 __AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000)
330 __AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000)
331 __AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000)
332 __AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000)
333 __AARCH64_INSN_FUNCS(store_imm, 0x3FC00000, 0x39000000)
334 __AARCH64_INSN_FUNCS(load_imm, 0x3FC00000, 0x39400000)
335 __AARCH64_INSN_FUNCS(store_pre, 0x3FE00C00, 0x38000C00)
336 __AARCH64_INSN_FUNCS(load_pre, 0x3FE00C00, 0x38400C00)
337 __AARCH64_INSN_FUNCS(store_post, 0x3FE00C00, 0x38000400)
338 __AARCH64_INSN_FUNCS(load_post, 0x3FE00C00, 0x38400400)
339 __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
340 __AARCH64_INSN_FUNCS(str_imm, 0x3FC00000, 0x39000000)
341 __AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
342 __AARCH64_INSN_FUNCS(ldclr, 0x3F20FC00, 0x38201000)
343 __AARCH64_INSN_FUNCS(ldeor, 0x3F20FC00, 0x38202000)
344 __AARCH64_INSN_FUNCS(ldset, 0x3F20FC00, 0x38203000)
345 __AARCH64_INSN_FUNCS(swp, 0x3F20FC00, 0x38208000)
346 __AARCH64_INSN_FUNCS(cas, 0x3FA07C00, 0x08A07C00)
347 __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
348 __AARCH64_INSN_FUNCS(ldr_imm, 0x3FC00000, 0x39400000)
349 __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000)
350 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
351 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
352 __AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000)
353 __AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000)
354 __AARCH64_INSN_FUNCS(stp, 0x7FC00000, 0x29000000)
355 __AARCH64_INSN_FUNCS(ldp, 0x7FC00000, 0x29400000)
356 __AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)
357 __AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000)
358 __AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000)
359 __AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000)
360 __AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000)
361 __AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000)
362 __AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000)
363 __AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000)
364 __AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000)
365 __AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000)
366 __AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000)
367 __AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000)
368 __AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000)
369 __AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000)
370 __AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000)
371 __AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000)
372 __AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000)
373 __AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000)
374 __AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000)
375 __AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000)
376 __AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800)
377 __AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
378 __AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000)
379 __AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400)
380 __AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800)
381 __AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
382 __AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
383 __AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
384 __AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
385 __AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
386 __AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
387 __AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
388 __AARCH64_INSN_FUNCS(mov_reg, 0x7FE0FFE0, 0x2A0003E0)
389 __AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
390 __AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
391 __AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
392 __AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
393 __AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
394 __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000)
395 __AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000)
396 __AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000)
397 __AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000)
398 __AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000)
399 __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
400 __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
401 __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
402 __AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
403 __AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
404 __AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
405 __AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
406 __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
407 __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
408 __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
409 __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
410 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
411 __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
412 __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000)
413 __AARCH64_INSN_FUNCS(br_auth, 0xFEFFF800, 0xD61F0800)
414 __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000)
415 __AARCH64_INSN_FUNCS(blr_auth, 0xFEFFF800, 0xD63F0800)
416 __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
417 __AARCH64_INSN_FUNCS(ret_auth, 0xFFFFFBFF, 0xD65F0BFF)
418 __AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0)
419 __AARCH64_INSN_FUNCS(eret_auth, 0xFFFFFBFF, 0xD69F0BFF)
420 __AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000)
421 __AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F)
422 __AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000)
423 __AARCH64_INSN_FUNCS(dmb, 0xFFFFF0FF, 0xD50330BF)
424 __AARCH64_INSN_FUNCS(dsb_base, 0xFFFFF0FF, 0xD503309F)
425 __AARCH64_INSN_FUNCS(dsb_nxs, 0xFFFFF3FF, 0xD503323F)
426 __AARCH64_INSN_FUNCS(isb, 0xFFFFF0FF, 0xD50330DF)
427 __AARCH64_INSN_FUNCS(sb, 0xFFFFFFFF, 0xD50330FF)
428 __AARCH64_INSN_FUNCS(clrex, 0xFFFFF0FF, 0xD503305F)
429 __AARCH64_INSN_FUNCS(ssbb, 0xFFFFFFFF, 0xD503309F)
430 __AARCH64_INSN_FUNCS(pssbb, 0xFFFFFFFF, 0xD503349F)
431
432 #undef __AARCH64_INSN_FUNCS
433
434 bool aarch64_insn_is_steppable_hint(u32 insn);
435 bool aarch64_insn_is_branch_imm(u32 insn);
436
aarch64_insn_is_adr_adrp(u32 insn)437 static inline bool aarch64_insn_is_adr_adrp(u32 insn)
438 {
439 return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn);
440 }
441
aarch64_insn_is_dsb(u32 insn)442 static inline bool aarch64_insn_is_dsb(u32 insn)
443 {
444 return aarch64_insn_is_dsb_base(insn) || aarch64_insn_is_dsb_nxs(insn);
445 }
446
aarch64_insn_is_barrier(u32 insn)447 static inline bool aarch64_insn_is_barrier(u32 insn)
448 {
449 return aarch64_insn_is_dmb(insn) || aarch64_insn_is_dsb(insn) ||
450 aarch64_insn_is_isb(insn) || aarch64_insn_is_sb(insn) ||
451 aarch64_insn_is_clrex(insn) || aarch64_insn_is_ssbb(insn) ||
452 aarch64_insn_is_pssbb(insn);
453 }
454
aarch64_insn_is_store_single(u32 insn)455 static inline bool aarch64_insn_is_store_single(u32 insn)
456 {
457 return aarch64_insn_is_store_imm(insn) ||
458 aarch64_insn_is_store_pre(insn) ||
459 aarch64_insn_is_store_post(insn);
460 }
461
aarch64_insn_is_store_pair(u32 insn)462 static inline bool aarch64_insn_is_store_pair(u32 insn)
463 {
464 return aarch64_insn_is_stp(insn) ||
465 aarch64_insn_is_stp_pre(insn) ||
466 aarch64_insn_is_stp_post(insn);
467 }
468
aarch64_insn_is_load_single(u32 insn)469 static inline bool aarch64_insn_is_load_single(u32 insn)
470 {
471 return aarch64_insn_is_load_imm(insn) ||
472 aarch64_insn_is_load_pre(insn) ||
473 aarch64_insn_is_load_post(insn);
474 }
475
aarch64_insn_is_load_pair(u32 insn)476 static inline bool aarch64_insn_is_load_pair(u32 insn)
477 {
478 return aarch64_insn_is_ldp(insn) ||
479 aarch64_insn_is_ldp_pre(insn) ||
480 aarch64_insn_is_ldp_post(insn);
481 }
482
483 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
484 bool aarch64_insn_uses_literal(u32 insn);
485 bool aarch64_insn_is_branch(u32 insn);
486 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
487 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
488 u32 insn, u64 imm);
489 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
490 u32 insn);
491 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
492 enum aarch64_insn_branch_type type);
493 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
494 enum aarch64_insn_register reg,
495 enum aarch64_insn_variant variant,
496 enum aarch64_insn_branch_type type);
497 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
498 enum aarch64_insn_condition cond);
499 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op);
500 u32 aarch64_insn_gen_nop(void);
501 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
502 enum aarch64_insn_branch_type type);
503 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
504 enum aarch64_insn_register base,
505 enum aarch64_insn_register offset,
506 enum aarch64_insn_size_type size,
507 enum aarch64_insn_ldst_type type);
508 u32 aarch64_insn_gen_load_store_imm(enum aarch64_insn_register reg,
509 enum aarch64_insn_register base,
510 unsigned int imm,
511 enum aarch64_insn_size_type size,
512 enum aarch64_insn_ldst_type type);
513 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
514 enum aarch64_insn_register reg2,
515 enum aarch64_insn_register base,
516 int offset,
517 enum aarch64_insn_variant variant,
518 enum aarch64_insn_ldst_type type);
519 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
520 enum aarch64_insn_register base,
521 enum aarch64_insn_register state,
522 enum aarch64_insn_size_type size,
523 enum aarch64_insn_ldst_type type);
524 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
525 enum aarch64_insn_register src,
526 int imm, enum aarch64_insn_variant variant,
527 enum aarch64_insn_adsb_type type);
528 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
529 enum aarch64_insn_register reg,
530 enum aarch64_insn_adr_type type);
531 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
532 enum aarch64_insn_register src,
533 int immr, int imms,
534 enum aarch64_insn_variant variant,
535 enum aarch64_insn_bitfield_type type);
536 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
537 int imm, int shift,
538 enum aarch64_insn_variant variant,
539 enum aarch64_insn_movewide_type type);
540 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
541 enum aarch64_insn_register src,
542 enum aarch64_insn_register reg,
543 int shift,
544 enum aarch64_insn_variant variant,
545 enum aarch64_insn_adsb_type type);
546 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
547 enum aarch64_insn_register src,
548 enum aarch64_insn_variant variant,
549 enum aarch64_insn_data1_type type);
550 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
551 enum aarch64_insn_register src,
552 enum aarch64_insn_register reg,
553 enum aarch64_insn_variant variant,
554 enum aarch64_insn_data2_type type);
555 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
556 enum aarch64_insn_register src,
557 enum aarch64_insn_register reg1,
558 enum aarch64_insn_register reg2,
559 enum aarch64_insn_variant variant,
560 enum aarch64_insn_data3_type type);
561 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
562 enum aarch64_insn_register src,
563 enum aarch64_insn_register reg,
564 int shift,
565 enum aarch64_insn_variant variant,
566 enum aarch64_insn_logic_type type);
567 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
568 enum aarch64_insn_register src,
569 enum aarch64_insn_variant variant);
570 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
571 enum aarch64_insn_variant variant,
572 enum aarch64_insn_register Rn,
573 enum aarch64_insn_register Rd,
574 u64 imm);
575 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
576 enum aarch64_insn_register Rm,
577 enum aarch64_insn_register Rn,
578 enum aarch64_insn_register Rd,
579 u8 lsb);
580 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
581 enum aarch64_insn_prfm_type type,
582 enum aarch64_insn_prfm_target target,
583 enum aarch64_insn_prfm_policy policy);
584 #ifdef CONFIG_ARM64_LSE_ATOMICS
585 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
586 enum aarch64_insn_register address,
587 enum aarch64_insn_register value,
588 enum aarch64_insn_size_type size,
589 enum aarch64_insn_mem_atomic_op op,
590 enum aarch64_insn_mem_order_type order);
591 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
592 enum aarch64_insn_register address,
593 enum aarch64_insn_register value,
594 enum aarch64_insn_size_type size,
595 enum aarch64_insn_mem_order_type order);
596 #else
597 static inline
aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size,enum aarch64_insn_mem_atomic_op op,enum aarch64_insn_mem_order_type order)598 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
599 enum aarch64_insn_register address,
600 enum aarch64_insn_register value,
601 enum aarch64_insn_size_type size,
602 enum aarch64_insn_mem_atomic_op op,
603 enum aarch64_insn_mem_order_type order)
604 {
605 return AARCH64_BREAK_FAULT;
606 }
607
608 static inline
aarch64_insn_gen_cas(enum aarch64_insn_register result,enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size,enum aarch64_insn_mem_order_type order)609 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
610 enum aarch64_insn_register address,
611 enum aarch64_insn_register value,
612 enum aarch64_insn_size_type size,
613 enum aarch64_insn_mem_order_type order)
614 {
615 return AARCH64_BREAK_FAULT;
616 }
617 #endif
618 u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
619
620 s32 aarch64_get_branch_offset(u32 insn);
621 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
622
623 s32 aarch64_insn_adrp_get_offset(u32 insn);
624 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
625
626 bool aarch32_insn_is_wide(u32 insn);
627
628 #define A32_RN_OFFSET 16
629 #define A32_RT_OFFSET 12
630 #define A32_RT2_OFFSET 0
631
632 u32 aarch64_insn_extract_system_reg(u32 insn);
633 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
634 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
635 u32 aarch32_insn_mcr_extract_crm(u32 insn);
636
637 typedef bool (pstate_check_t)(unsigned long);
638 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
639
640 #endif /* __ASSEMBLY__ */
641
642 #endif /* __ASM_INSN_H */
643