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Searched refs:vuip (Results 1 – 24 of 24) sorted by relevance

/linux-3.4.99/arch/alpha/kernel/
Dcore_apecs.c47 #define vuip volatile unsigned int * macro
137 stat0 = *(vuip)APECS_IOC_DCSR; in conf_read()
138 *(vuip)APECS_IOC_DCSR = stat0; in conf_read()
144 haxr2 = *(vuip)APECS_IOC_HAXR2; in conf_read()
146 *(vuip)APECS_IOC_HAXR2 = haxr2 | 1; in conf_read()
158 asm volatile("ldl %0,%1; mb; mb" : "=r"(value) : "m"(*(vuip)addr) in conf_read()
179 stat0 = *(vuip)APECS_IOC_DCSR; in conf_read()
190 *(vuip)APECS_IOC_DCSR = stat0; in conf_read()
199 *(vuip)APECS_IOC_HAXR2 = haxr2 & ~1; in conf_read()
217 stat0 = *(vuip)APECS_IOC_DCSR; in conf_write()
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Dcore_mcpcia.c101 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()
102 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; in conf_read()
104 *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()
115 value = *((vuip)addr); in conf_read()
146 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()
147 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); in conf_write()
148 *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()
157 *((vuip)addr) = value; in conf_write()
160 *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */ in conf_write()
248 *(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0; in mcpcia_pci_tbi()
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Dsys_alcor.c41 *(vuip)GRU_INT_MASK = mask; in alcor_update_irq_hw()
63 *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb(); in alcor_mask_and_ack_irq()
64 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_mask_and_ack_irq()
73 *(vuip)GRU_INT_CLEAR = 0x80000000; mb(); in alcor_isa_mask_and_ack_irq()
74 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_isa_mask_and_ack_irq()
91 pld = (*(vuip)GRU_INT_REQ) & GRU_INT_REQ_BITS; in alcor_device_interrupt()
116 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ in alcor_init_irq()
117 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ in alcor_init_irq()
118 *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ in alcor_init_irq()
119 *(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */ in alcor_init_irq()
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Dsys_rawhide.c49 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask; in rawhide_update_irq_hw()
51 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)); in rawhide_update_irq_hw()
121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()
177 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; in rawhide_init_irq()
178 *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0; in rawhide_init_irq()
Dcore_polaris.c100 *value = *(vuip)addr; in polaris_read_config()
130 *(vuip)addr = value; in polaris_write_config()
132 *(vuip)addr; in polaris_write_config()
Dcore_irongate.c120 *value = *(vuip)addr; in irongate_read_config()
149 *(vuip)addr = value; in irongate_write_config()
151 *(vuip)addr; in irongate_write_config()
Dcore_tsunami.c132 *value = *(vuip)addr; in tsunami_read_config()
161 *(vuip)addr = value; in tsunami_write_config()
163 *(vuip)addr; in tsunami_write_config()
Dirq_pyxis.c100 *(vuip) CIA_IACK_SC; in init_pyxis_irqs()
Dcore_marvel.c550 *value = *(vuip)addr; in marvel_read_config()
580 *(vuip)addr = value; in marvel_write_config()
582 *(vuip)addr; in marvel_write_config()
1078 vuip addr; in marvel_agp_info()
1084 addr = (vuip)build_conf_addr(h, 0, PCI_DEVFN(5, 0), 0); in marvel_agp_info()
Dirq_i8259.c132 int j = *(vuip) IACK_SC; in isa_device_interrupt()
Dcore_lca.c142 value = *(vuip)addr; in conf_read()
179 *(vuip)addr = value; in conf_write()
Dsys_ruffian.c94 *(vuip) PYXIS_RESET = 0x0000dead; in ruffian_kill_arch()
Dsys_miata.c251 *(vuip) PYXIS_RESET = 0x0000dead; in miata_kill_arch()
Dcore_wildfire.c396 *value = *(vuip)addr; in wildfire_read_config()
425 *(vuip)addr = value; in wildfire_write_config()
427 *(vuip)addr; in wildfire_write_config()
Dcore_t2.c204 value = *(vuip)addr; in conf_read()
256 *(vuip)addr = value; in conf_write()
Dcore_titan.c156 *value = *(vuip)addr; in titan_read_config()
185 *(vuip)addr = value; in titan_write_config()
187 *(vuip)addr; in titan_write_config()
Dproto.h11 #define vuip volatile unsigned int * macro
Dsetup.c1371 car = *(vuip) phys_to_virt (0x120000078UL); in determine_cpu_caches()
/linux-3.4.99/arch/alpha/include/asm/
Djensen.h99 #define vuip volatile unsigned int * macro
115 return 0xff & *(vuip)((addr << 9) + EISA_VL82C106); in jensen_local_inb()
120 *(vuip)((addr << 9) + EISA_VL82C106) = b; in jensen_local_outb()
136 *(vuip)((addr << 7) + EISA_IO + 0x00) = b * 0x01010101; in jensen_bus_outb()
182 return *(vuip) ((addr << 7) + EISA_IO + 0x60); in jensen_inl()
188 *(vuip) ((addr << 7) + EISA_IO + 0x20) = b * 0x00010001; in jensen_outw()
195 *(vuip) ((addr << 7) + EISA_IO + 0x60) = b; in jensen_outl()
232 return *(vuip) ((addr << 7) + EISA_MEM + 0x60); in jensen_readl()
243 r0 = *(vuip) (addr); in jensen_readq()
244 r1 = *(vuip) (addr + (4 << 7)); in jensen_readq()
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Dcore_t2.h361 #define vuip volatile unsigned int * macro
374 *(vuip) ((addr << 5) + T2_IO + 0x00) = w; in t2_outb()
389 *(vuip) ((addr << 5) + T2_IO + 0x08) = w; in t2_outw()
395 return *(vuip) ((addr << 5) + T2_IO + 0x18); in t2_inl()
400 *(vuip) ((addr << 5) + T2_IO + 0x18) = b; in t2_outl()
470 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); in t2_readw()
485 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); in t2_readl()
497 r0 = *(vuip)(work); in t2_readq()
498 r1 = *(vuip)(work + (4 << 5)); in t2_readq()
510 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w; in t2_writeb()
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Dcore_lca.h219 #define vuip volatile unsigned int __force * macro
265 *(vuip) ((addr << 5) + base_and_type) = w; in lca_iowrite8()
301 *(vuip) ((addr << 5) + base_and_type) = w; in lca_iowrite16()
309 return *(vuip)addr; in lca_ioread32()
317 *(vuip)addr = b; in lca_iowrite32()
342 #undef vuip
Dcore_mcpcia.h249 #define vuip volatile unsigned int __force * macro
290 *(vuip) ((addr << 5) + hose + 0x00) = w; in mcpcia_iowrite8()
314 *(vuip) ((addr << 5) + hose + 0x08) = w; in mcpcia_iowrite16()
324 return *(vuip)addr; in mcpcia_ioread32()
334 *(vuip)addr = b; in mcpcia_iowrite32()
363 #undef vuip
Dcore_cia.h341 #define vuip volatile unsigned int __force * macro
373 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite8()
403 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite16()
411 return *(vuip)addr; in cia_ioread32()
419 *(vuip)addr = b; in cia_iowrite32()
465 #undef vuip
Dcore_apecs.h374 #define vuip volatile unsigned int __force * macro
419 *(vuip) ((addr << 5) + base_and_type) = w; in apecs_iowrite8()
455 *(vuip) ((addr << 5) + base_and_type) = w; in apecs_iowrite16()
463 return *(vuip)addr; in apecs_ioread32()
471 *(vuip)addr = b; in apecs_iowrite32()
498 #undef vuip