Searched refs:spll_clk (Results 1 – 2 of 2) sorted by relevance
479 static struct clk spll_clk = { variable589 DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);694 ssi1_clk.parent = &spll_clk; in to2_adjust_clocks()697 ssi1_clk.parent = &spll_clk; in to2_adjust_clocks()700 vpu_clk.parent = &spll_clk; in to2_adjust_clocks()737 spll_clk.parent = &ckih_clk; in mx27_clocks_init()739 spll_clk.parent = &fpm_clk; in mx27_clocks_init()749 spll_clk.disable(&spll_clk); in mx27_clocks_init()
556 static struct clk spll_clk = { variable861 .parent = &spll_clk,1097 else if (parent == spll_clk.parent) in _clk_clko_set_parent()1101 else if (parent == &spll_clk) in _clk_clko_set_parent()1215 spll_clk.parent = &ckih_clk; in mx21_clocks_init()1217 spll_clk.parent = &fpm_clk; in mx21_clocks_init()1226 spll_clk.disable(&spll_clk); in mx21_clocks_init()