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Searched refs:speed_cntl (Results 1 – 3 of 3) sorted by relevance

/linux-3.4.99/drivers/gpu/drm/radeon/
Drv770.c1307 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
1340 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
1341 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in rv770_pcie_gen2_enable()
1342 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in rv770_pcie_gen2_enable()
1353 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
1354 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in rv770_pcie_gen2_enable()
1355 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in rv770_pcie_gen2_enable()
1357 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
1358 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; in rv770_pcie_gen2_enable()
1359 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in rv770_pcie_gen2_enable()
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Devergreen.c3502 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
3517 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
3518 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || in evergreen_pcie_gen2_enable()
3519 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in evergreen_pcie_gen2_enable()
3525 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
3526 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in evergreen_pcie_gen2_enable()
3527 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in evergreen_pcie_gen2_enable()
3529 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
3530 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; in evergreen_pcie_gen2_enable()
3531 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in evergreen_pcie_gen2_enable()
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Dr600.c3705 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
3746 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
3747 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in r600_pcie_gen2_enable()
3748 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in r600_pcie_gen2_enable()
3762 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; in r600_pcie_gen2_enable()
3763 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); in r600_pcie_gen2_enable()
3764 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; in r600_pcie_gen2_enable()
3765 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
3766 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
3767 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in r600_pcie_gen2_enable()
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