1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43
44 #include <linux/mlx4/device.h>
45 #include <linux/mlx4/qp.h>
46 #include <linux/mlx4/cq.h>
47 #include <linux/mlx4/srq.h>
48 #include <linux/mlx4/doorbell.h>
49 #include <linux/mlx4/cmd.h>
50
51 #include "en_port.h"
52
53 #define DRV_NAME "mlx4_en"
54 #define DRV_VERSION "2.0"
55 #define DRV_RELDATE "Dec 2011"
56
57 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
58
59 /*
60 * Device constants
61 */
62
63
64 #define MLX4_EN_PAGE_SHIFT 12
65 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
66 #define MAX_RX_RINGS 16
67 #define MIN_RX_RINGS 4
68 #define TXBB_SIZE 64
69 #define HEADROOM (2048 / TXBB_SIZE + 1)
70 #define STAMP_STRIDE 64
71 #define STAMP_DWORDS (STAMP_STRIDE / 4)
72 #define STAMP_SHIFT 31
73 #define STAMP_VAL 0x7fffffff
74 #define STATS_DELAY (HZ / 4)
75
76 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
77 #define MAX_DESC_SIZE 512
78 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
79
80 /*
81 * OS related constants and tunables
82 */
83
84 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
85
86 /* Use the maximum between 16384 and a single page */
87 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
88 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
89
90 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32
91
92 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
93 * and 4K allocations) */
94 enum {
95 FRAG_SZ0 = 512 - NET_IP_ALIGN,
96 FRAG_SZ1 = 1024,
97 FRAG_SZ2 = 4096,
98 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
99 };
100 #define MLX4_EN_MAX_RX_FRAGS 4
101
102 /* Maximum ring sizes */
103 #define MLX4_EN_MAX_TX_SIZE 8192
104 #define MLX4_EN_MAX_RX_SIZE 8192
105
106 /* Minimum ring size for our page-allocation sceme to work */
107 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
108 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
109
110 #define MLX4_EN_SMALL_PKT_SIZE 64
111 #define MLX4_EN_NUM_TX_RINGS 8
112 #define MLX4_EN_NUM_PPP_RINGS 8
113 #define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
114 #define MLX4_EN_DEF_TX_RING_SIZE 512
115 #define MLX4_EN_DEF_RX_RING_SIZE 1024
116
117 /* Target number of packets to coalesce with interrupt moderation */
118 #define MLX4_EN_RX_COAL_TARGET 44
119 #define MLX4_EN_RX_COAL_TIME 0x10
120
121 #define MLX4_EN_TX_COAL_PKTS 5
122 #define MLX4_EN_TX_COAL_TIME 0x80
123
124 #define MLX4_EN_RX_RATE_LOW 400000
125 #define MLX4_EN_RX_COAL_TIME_LOW 0
126 #define MLX4_EN_RX_RATE_HIGH 450000
127 #define MLX4_EN_RX_COAL_TIME_HIGH 128
128 #define MLX4_EN_RX_SIZE_THRESH 1024
129 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
130 #define MLX4_EN_SAMPLE_INTERVAL 0
131 #define MLX4_EN_AVG_PKT_SMALL 256
132
133 #define MLX4_EN_AUTO_CONF 0xffff
134
135 #define MLX4_EN_DEF_RX_PAUSE 1
136 #define MLX4_EN_DEF_TX_PAUSE 1
137
138 /* Interval between successive polls in the Tx routine when polling is used
139 instead of interrupts (in per-core Tx rings) - should be power of 2 */
140 #define MLX4_EN_TX_POLL_MODER 16
141 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
142
143 #define ETH_LLC_SNAP_SIZE 8
144
145 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
146 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
147 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
148
149 #define MLX4_EN_MIN_MTU 46
150 #define ETH_BCAST 0xffffffffffffULL
151
152 #define MLX4_EN_LOOPBACK_RETRIES 5
153 #define MLX4_EN_LOOPBACK_TIMEOUT 100
154
155 #ifdef MLX4_EN_PERF_STAT
156 /* Number of samples to 'average' */
157 #define AVG_SIZE 128
158 #define AVG_FACTOR 1024
159 #define NUM_PERF_STATS NUM_PERF_COUNTERS
160
161 #define INC_PERF_COUNTER(cnt) (++(cnt))
162 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
163 #define AVG_PERF_COUNTER(cnt, sample) \
164 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
165 #define GET_PERF_COUNTER(cnt) (cnt)
166 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
167
168 #else
169
170 #define NUM_PERF_STATS 0
171 #define INC_PERF_COUNTER(cnt) do {} while (0)
172 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
173 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
174 #define GET_PERF_COUNTER(cnt) (0)
175 #define GET_AVG_PERF_COUNTER(cnt) (0)
176 #endif /* MLX4_EN_PERF_STAT */
177
178 /*
179 * Configurables
180 */
181
182 enum cq_type {
183 RX = 0,
184 TX = 1,
185 };
186
187
188 /*
189 * Useful macros
190 */
191 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
192 #define XNOR(x, y) (!(x) == !(y))
193 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
194
195
196 struct mlx4_en_tx_info {
197 struct sk_buff *skb;
198 u32 nr_txbb;
199 u8 linear;
200 u8 data_offset;
201 u8 inl;
202 };
203
204
205 #define MLX4_EN_BIT_DESC_OWN 0x80000000
206 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
207 #define MLX4_EN_MEMTYPE_PAD 0x100
208 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
209
210
211 struct mlx4_en_tx_desc {
212 struct mlx4_wqe_ctrl_seg ctrl;
213 union {
214 struct mlx4_wqe_data_seg data; /* at least one data segment */
215 struct mlx4_wqe_lso_seg lso;
216 struct mlx4_wqe_inline_seg inl;
217 };
218 };
219
220 #define MLX4_EN_USE_SRQ 0x01000000
221
222 #define MLX4_EN_CX3_LOW_ID 0x1000
223 #define MLX4_EN_CX3_HIGH_ID 0x1005
224
225 struct mlx4_en_rx_alloc {
226 struct page *page;
227 u16 offset;
228 };
229
230 struct mlx4_en_tx_ring {
231 struct mlx4_hwq_resources wqres;
232 u32 size ; /* number of TXBBs */
233 u32 size_mask;
234 u16 stride;
235 u16 cqn; /* index of port CQ associated with this ring */
236 u32 prod;
237 u32 cons;
238 u32 buf_size;
239 u32 doorbell_qpn;
240 void *buf;
241 u16 poll_cnt;
242 int blocked;
243 struct mlx4_en_tx_info *tx_info;
244 u8 *bounce_buf;
245 u32 last_nr_txbb;
246 struct mlx4_qp qp;
247 struct mlx4_qp_context context;
248 int qpn;
249 enum mlx4_qp_state qp_state;
250 struct mlx4_srq dummy;
251 unsigned long bytes;
252 unsigned long packets;
253 unsigned long tx_csum;
254 spinlock_t comp_lock;
255 struct mlx4_bf bf;
256 bool bf_enabled;
257 };
258
259 struct mlx4_en_rx_desc {
260 /* actual number of entries depends on rx ring stride */
261 struct mlx4_wqe_data_seg data[0];
262 };
263
264 struct mlx4_en_rx_ring {
265 struct mlx4_hwq_resources wqres;
266 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
267 u32 size ; /* number of Rx descs*/
268 u32 actual_size;
269 u32 size_mask;
270 u16 stride;
271 u16 log_stride;
272 u16 cqn; /* index of port CQ associated with this ring */
273 u32 prod;
274 u32 cons;
275 u32 buf_size;
276 u8 fcs_del;
277 void *buf;
278 void *rx_info;
279 unsigned long bytes;
280 unsigned long packets;
281 unsigned long csum_ok;
282 unsigned long csum_none;
283 };
284
285
mlx4_en_can_lro(__be16 status)286 static inline int mlx4_en_can_lro(__be16 status)
287 {
288 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
289 MLX4_CQE_STATUS_IPV4F |
290 MLX4_CQE_STATUS_IPV6 |
291 MLX4_CQE_STATUS_IPV4OPT |
292 MLX4_CQE_STATUS_TCP |
293 MLX4_CQE_STATUS_UDP |
294 MLX4_CQE_STATUS_IPOK)) ==
295 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
296 MLX4_CQE_STATUS_IPOK |
297 MLX4_CQE_STATUS_TCP);
298 }
299
300 struct mlx4_en_cq {
301 struct mlx4_cq mcq;
302 struct mlx4_hwq_resources wqres;
303 int ring;
304 struct net_device *dev;
305 struct napi_struct napi;
306 /* Per-core Tx cq processing support */
307 struct timer_list timer;
308 int size;
309 int buf_size;
310 unsigned vector;
311 enum cq_type is_tx;
312 u16 moder_time;
313 u16 moder_cnt;
314 struct mlx4_cqe *buf;
315 #define MLX4_EN_OPCODE_ERROR 0x1e
316 };
317
318 struct mlx4_en_port_profile {
319 u32 flags;
320 u32 tx_ring_num;
321 u32 rx_ring_num;
322 u32 tx_ring_size;
323 u32 rx_ring_size;
324 u8 rx_pause;
325 u8 rx_ppp;
326 u8 tx_pause;
327 u8 tx_ppp;
328 int rss_rings;
329 };
330
331 struct mlx4_en_profile {
332 int rss_xor;
333 int udp_rss;
334 u8 rss_mask;
335 u32 active_ports;
336 u32 small_pkt_int;
337 u8 no_reset;
338 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
339 };
340
341 struct mlx4_en_dev {
342 struct mlx4_dev *dev;
343 struct pci_dev *pdev;
344 struct mutex state_lock;
345 struct net_device *pndev[MLX4_MAX_PORTS + 1];
346 u32 port_cnt;
347 bool device_up;
348 struct mlx4_en_profile profile;
349 u32 LSO_support;
350 struct workqueue_struct *workqueue;
351 struct device *dma_device;
352 void __iomem *uar_map;
353 struct mlx4_uar priv_uar;
354 struct mlx4_mr mr;
355 u32 priv_pdn;
356 spinlock_t uar_lock;
357 u8 mac_removed[MLX4_MAX_PORTS + 1];
358 };
359
360
361 struct mlx4_en_rss_map {
362 int base_qpn;
363 struct mlx4_qp qps[MAX_RX_RINGS];
364 enum mlx4_qp_state state[MAX_RX_RINGS];
365 struct mlx4_qp indir_qp;
366 enum mlx4_qp_state indir_state;
367 };
368
369 struct mlx4_en_port_state {
370 int link_state;
371 int link_speed;
372 int transciver;
373 };
374
375 struct mlx4_en_pkt_stats {
376 unsigned long broadcast;
377 unsigned long rx_prio[8];
378 unsigned long tx_prio[8];
379 #define NUM_PKT_STATS 17
380 };
381
382 struct mlx4_en_port_stats {
383 unsigned long tso_packets;
384 unsigned long queue_stopped;
385 unsigned long wake_queue;
386 unsigned long tx_timeout;
387 unsigned long rx_alloc_failed;
388 unsigned long rx_chksum_good;
389 unsigned long rx_chksum_none;
390 unsigned long tx_chksum_offload;
391 #define NUM_PORT_STATS 8
392 };
393
394 struct mlx4_en_perf_stats {
395 u32 tx_poll;
396 u64 tx_pktsz_avg;
397 u32 inflight_avg;
398 u16 tx_coal_avg;
399 u16 rx_coal_avg;
400 u32 napi_quota;
401 #define NUM_PERF_COUNTERS 6
402 };
403
404 struct mlx4_en_frag_info {
405 u16 frag_size;
406 u16 frag_prefix_size;
407 u16 frag_stride;
408 u16 frag_align;
409 u16 last_offset;
410
411 };
412
413 struct mlx4_en_priv {
414 struct mlx4_en_dev *mdev;
415 struct mlx4_en_port_profile *prof;
416 struct net_device *dev;
417 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
418 struct net_device_stats stats;
419 struct net_device_stats ret_stats;
420 struct mlx4_en_port_state port_state;
421 spinlock_t stats_lock;
422
423 unsigned long last_moder_packets[MAX_RX_RINGS];
424 unsigned long last_moder_tx_packets;
425 unsigned long last_moder_bytes[MAX_RX_RINGS];
426 unsigned long last_moder_jiffies;
427 int last_moder_time[MAX_RX_RINGS];
428 u16 rx_usecs;
429 u16 rx_frames;
430 u16 tx_usecs;
431 u16 tx_frames;
432 u32 pkt_rate_low;
433 u16 rx_usecs_low;
434 u32 pkt_rate_high;
435 u16 rx_usecs_high;
436 u16 sample_interval;
437 u16 adaptive_rx_coal;
438 u32 msg_enable;
439 u32 loopback_ok;
440 u32 validate_loopback;
441
442 struct mlx4_hwq_resources res;
443 int link_state;
444 int last_link_state;
445 bool port_up;
446 int port;
447 int registered;
448 int allocated;
449 int stride;
450 u64 mac;
451 int mac_index;
452 unsigned max_mtu;
453 int base_qpn;
454
455 struct mlx4_en_rss_map rss_map;
456 __be32 ctrl_flags;
457 u32 flags;
458 #define MLX4_EN_FLAG_PROMISC 0x1
459 #define MLX4_EN_FLAG_MC_PROMISC 0x2
460 u32 tx_ring_num;
461 u32 rx_ring_num;
462 u32 rx_skb_size;
463 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
464 u16 num_frags;
465 u16 log_rx_info;
466
467 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
468 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
469 struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
470 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
471 struct work_struct mcast_task;
472 struct work_struct mac_task;
473 struct work_struct watchdog_task;
474 struct work_struct linkstate_task;
475 struct delayed_work stats_task;
476 struct mlx4_en_perf_stats pstats;
477 struct mlx4_en_pkt_stats pkstats;
478 struct mlx4_en_port_stats port_stats;
479 u64 stats_bitmap;
480 char *mc_addrs;
481 int mc_addrs_cnt;
482 struct mlx4_en_stat_out_mbox hw_stats;
483 int vids[128];
484 bool wol;
485 struct device *ddev;
486 };
487
488 enum mlx4_en_wol {
489 MLX4_EN_WOL_MAGIC = (1ULL << 61),
490 MLX4_EN_WOL_ENABLED = (1ULL << 62),
491 };
492
493 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
494
495 void mlx4_en_destroy_netdev(struct net_device *dev);
496 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
497 struct mlx4_en_port_profile *prof);
498
499 int mlx4_en_start_port(struct net_device *dev);
500 void mlx4_en_stop_port(struct net_device *dev);
501
502 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
503 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
504
505 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
506 int entries, int ring, enum cq_type mode);
507 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
508 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
509 int cq_idx);
510 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
511 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
512 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
513
514 void mlx4_en_poll_tx_cq(unsigned long data);
515 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
516 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
517 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
518
519 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
520 int qpn, u32 size, u16 stride);
521 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
522 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
523 struct mlx4_en_tx_ring *ring,
524 int cq);
525 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
526 struct mlx4_en_tx_ring *ring);
527
528 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
529 struct mlx4_en_rx_ring *ring,
530 u32 size, u16 stride);
531 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
532 struct mlx4_en_rx_ring *ring,
533 u32 size, u16 stride);
534 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
535 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
536 struct mlx4_en_rx_ring *ring);
537 int mlx4_en_process_rx_cq(struct net_device *dev,
538 struct mlx4_en_cq *cq,
539 int budget);
540 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
541 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
542 int is_tx, int rss, int qpn, int cqn,
543 struct mlx4_qp_context *context);
544 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
545 int mlx4_en_map_buffer(struct mlx4_buf *buf);
546 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
547
548 void mlx4_en_calc_rx_buf(struct net_device *dev);
549 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
550 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
551 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
552 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
553
554 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
555 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
556
557 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
558 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
559
560 #define MLX4_EN_NUM_SELF_TEST 5
561 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
562 u64 mlx4_en_mac_to_u64(u8 *addr);
563
564 /*
565 * Globals
566 */
567 extern const struct ethtool_ops mlx4_en_ethtool_ops;
568
569
570
571 /*
572 * printk / logging functions
573 */
574
575 __printf(3, 4)
576 int en_print(const char *level, const struct mlx4_en_priv *priv,
577 const char *format, ...);
578
579 #define en_dbg(mlevel, priv, format, arg...) \
580 do { \
581 if (NETIF_MSG_##mlevel & priv->msg_enable) \
582 en_print(KERN_DEBUG, priv, format, ##arg); \
583 } while (0)
584 #define en_warn(priv, format, arg...) \
585 en_print(KERN_WARNING, priv, format, ##arg)
586 #define en_err(priv, format, arg...) \
587 en_print(KERN_ERR, priv, format, ##arg)
588 #define en_info(priv, format, arg...) \
589 en_print(KERN_INFO, priv, format, ## arg)
590
591 #define mlx4_err(mdev, format, arg...) \
592 pr_err("%s %s: " format, DRV_NAME, \
593 dev_name(&mdev->pdev->dev), ##arg)
594 #define mlx4_info(mdev, format, arg...) \
595 pr_info("%s %s: " format, DRV_NAME, \
596 dev_name(&mdev->pdev->dev), ##arg)
597 #define mlx4_warn(mdev, format, arg...) \
598 pr_warning("%s %s: " format, DRV_NAME, \
599 dev_name(&mdev->pdev->dev), ##arg)
600
601 #endif
602