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Searched refs:reg_div (Results 1 – 15 of 15) sorted by relevance

/linux-3.4.99/arch/arm/plat-samsung/
Dclock-clksrc.c42 u32 clkdiv = __raw_readl(sclk->reg_div.reg); in s3c_getrate_clksrc()
43 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); in s3c_getrate_clksrc()
46 clkdiv >>= sclk->reg_div.shift; in s3c_getrate_clksrc()
56 void __iomem *reg = sclk->reg_div.reg; in s3c_setrate_clksrc()
58 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); in s3c_setrate_clksrc()
63 if (div > (1 << sclk->reg_div.size)) in s3c_setrate_clksrc()
68 val |= (div - 1) << sclk->reg_div.shift; in s3c_setrate_clksrc()
107 int max_div = 1 << sclk->reg_div.size; in s3c_roundrate_clksrc()
183 if (!clksrc->reg_div.reg && !clksrc->reg_src.reg) in s3c_register_clksrc()
190 if (!clksrc->reg_div.reg) in s3c_register_clksrc()
/linux-3.4.99/arch/arm/mach-exynos/
Dclock-exynos4.c226 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
269 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
284 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
292 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
300 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
308 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
336 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
344 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
352 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
360 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
[all …]
Dclock-exynos5.c145 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
241 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
310 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
318 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
344 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
352 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
360 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
381 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
400 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
409 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
[all …]
Dclock-exynos4210.c65 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
75 .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
/linux-3.4.99/Documentation/arm/Samsung/
Dclksrc-change-registers.awk92 reg_div=""
109 reg_div = extract_value(line)
125 printf "rdiv '" reg_div "'\n" > "/dev/stderr"
130 sub(reg_src, reg_div, generated)
134 printf "/* rdiv " reg_div " */\n"
140 if (reg_div != "") {
142 printf ".reg = " reg_div ", "
/linux-3.4.99/arch/arm/mach-s5p64x0/
Dclock-s5p6450.c101 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
128 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
136 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
143 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
151 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
160 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
168 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
411 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
423 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
432 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
[all …]
Dclock-s5p6440.c101 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
109 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
117 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
125 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
389 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
398 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
407 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
416 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
429 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
441 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
[all …]
Dclock.c165 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
174 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
/linux-3.4.99/arch/arm/mach-s5pv210/
Dclock.c77 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
85 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
93 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
101 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
120 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
128 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
137 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
285 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
633 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
[all …]
/linux-3.4.99/arch/arm/mach-s5pc100/
Dclock.c125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
133 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
141 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
149 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
157 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
165 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
191 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
199 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
207 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
233 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
[all …]
/linux-3.4.99/arch/arm/mach-s3c24xx/
Dclock-s3c2416.c54 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
80 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
88 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
Dclock-s3c2443.c91 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
108 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
Dcommon-s3c2443.c339 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
353 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
361 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
371 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
389 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
/linux-3.4.99/arch/arm/mach-s3c64xx/
Dclock.c701 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
711 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
721 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
731 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
740 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
748 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
762 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
774 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
786 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
798 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
[all …]
/linux-3.4.99/arch/arm/plat-samsung/include/plat/
Dclock-clksrc.h63 struct clksrc_reg reg_div; member