1 #ifndef __clkgen_defs_asm_h 2 #define __clkgen_defs_asm_h 3 4 /* 5 * This file is autogenerated from 6 * file: clkgen.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13 14 #ifndef REG_FIELD 15 #define REG_FIELD( scope, reg, field, value ) \ 16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 17 #define REG_FIELD_X_( value, shift ) ((value) << shift) 18 #endif 19 20 #ifndef REG_STATE 21 #define REG_STATE( scope, reg, field, symbolic_value ) \ 22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 23 #define REG_STATE_X_( k, shift ) (k << shift) 24 #endif 25 26 #ifndef REG_MASK 27 #define REG_MASK( scope, reg, field ) \ 28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 29 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 30 #endif 31 32 #ifndef REG_LSB 33 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 34 #endif 35 36 #ifndef REG_BIT 37 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 38 #endif 39 40 #ifndef REG_ADDR 41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) 43 #endif 44 45 #ifndef REG_ADDR_VECT 46 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 48 STRIDE_##scope##_##reg ) 49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 50 ((inst) + offs + (index) * stride) 51 #endif 52 53 /* Register r_bootsel, scope clkgen, type r */ 54 #define reg_clkgen_r_bootsel___boot_mode___lsb 0 55 #define reg_clkgen_r_bootsel___boot_mode___width 5 56 #define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 57 #define reg_clkgen_r_bootsel___intern_main_clk___width 1 58 #define reg_clkgen_r_bootsel___intern_main_clk___bit 5 59 #define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 60 #define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 61 #define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 62 #define reg_clkgen_r_bootsel_offset 0 63 64 /* Register rw_clk_ctrl, scope clkgen, type rw */ 65 #define reg_clkgen_rw_clk_ctrl___pll___lsb 0 66 #define reg_clkgen_rw_clk_ctrl___pll___width 1 67 #define reg_clkgen_rw_clk_ctrl___pll___bit 0 68 #define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 69 #define reg_clkgen_rw_clk_ctrl___cpu___width 1 70 #define reg_clkgen_rw_clk_ctrl___cpu___bit 1 71 #define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 72 #define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 73 #define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 74 #define reg_clkgen_rw_clk_ctrl___vin___lsb 3 75 #define reg_clkgen_rw_clk_ctrl___vin___width 1 76 #define reg_clkgen_rw_clk_ctrl___vin___bit 3 77 #define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 78 #define reg_clkgen_rw_clk_ctrl___sclr___width 1 79 #define reg_clkgen_rw_clk_ctrl___sclr___bit 4 80 #define reg_clkgen_rw_clk_ctrl___h264___lsb 5 81 #define reg_clkgen_rw_clk_ctrl___h264___width 1 82 #define reg_clkgen_rw_clk_ctrl___h264___bit 5 83 #define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 84 #define reg_clkgen_rw_clk_ctrl___ddr2___width 1 85 #define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 86 #define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 87 #define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 88 #define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 89 #define reg_clkgen_rw_clk_ctrl___eth___lsb 8 90 #define reg_clkgen_rw_clk_ctrl___eth___width 1 91 #define reg_clkgen_rw_clk_ctrl___eth___bit 8 92 #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 93 #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 94 #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 95 #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 96 #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 97 #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 98 #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 99 #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 100 #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 101 #define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 102 #define reg_clkgen_rw_clk_ctrl___jpeg___width 1 103 #define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 104 #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 105 #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 106 #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 107 #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 108 #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 109 #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 110 #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 111 #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 112 #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 113 #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 114 #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 115 #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 116 #define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 117 #define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 118 #define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 119 #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 120 #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 121 #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 122 #define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 123 #define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 124 #define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 125 #define reg_clkgen_rw_clk_ctrl_offset 4 126 127 128 /* Constants */ 129 #define regk_clkgen_eth1000_rx 0x0000000c 130 #define regk_clkgen_eth1000_tx 0x0000000e 131 #define regk_clkgen_eth100_rx 0x0000001d 132 #define regk_clkgen_eth100_rx_half 0x0000001c 133 #define regk_clkgen_eth100_tx 0x0000001f 134 #define regk_clkgen_eth100_tx_half 0x0000001e 135 #define regk_clkgen_nand_3_2 0x00000000 136 #define regk_clkgen_nand_3_2_0x30 0x00000002 137 #define regk_clkgen_nand_3_2_0x30_pll 0x00000012 138 #define regk_clkgen_nand_3_2_pll 0x00000010 139 #define regk_clkgen_nand_3_3 0x00000001 140 #define regk_clkgen_nand_3_3_0x30 0x00000003 141 #define regk_clkgen_nand_3_3_0x30_pll 0x00000013 142 #define regk_clkgen_nand_3_3_pll 0x00000011 143 #define regk_clkgen_nand_4_2 0x00000004 144 #define regk_clkgen_nand_4_2_0x30 0x00000006 145 #define regk_clkgen_nand_4_2_0x30_pll 0x00000016 146 #define regk_clkgen_nand_4_2_pll 0x00000014 147 #define regk_clkgen_nand_4_3 0x00000005 148 #define regk_clkgen_nand_4_3_0x30 0x00000007 149 #define regk_clkgen_nand_4_3_0x30_pll 0x00000017 150 #define regk_clkgen_nand_4_3_pll 0x00000015 151 #define regk_clkgen_nand_5_2 0x00000008 152 #define regk_clkgen_nand_5_2_0x30 0x0000000a 153 #define regk_clkgen_nand_5_2_0x30_pll 0x0000001a 154 #define regk_clkgen_nand_5_2_pll 0x00000018 155 #define regk_clkgen_nand_5_3 0x00000009 156 #define regk_clkgen_nand_5_3_0x30 0x0000000b 157 #define regk_clkgen_nand_5_3_0x30_pll 0x0000001b 158 #define regk_clkgen_nand_5_3_pll 0x00000019 159 #define regk_clkgen_no 0x00000000 160 #define regk_clkgen_rw_clk_ctrl_default 0x00000002 161 #define regk_clkgen_ser 0x0000000d 162 #define regk_clkgen_ser_pll 0x0000000f 163 #define regk_clkgen_yes 0x00000001 164 #endif /* __clkgen_defs_asm_h */ 165