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Searched refs:radeon_ring_write (Results 1 – 13 of 13) sorted by relevance

/linux-3.4.99/drivers/gpu/drm/radeon/
Devergreen_blit_kms.c56 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15)); in set_render_target()
57 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2); in set_render_target()
58 radeon_ring_write(ring, gpu_addr >> 8); in set_render_target()
59 radeon_ring_write(ring, pitch); in set_render_target()
60 radeon_ring_write(ring, slice); in set_render_target()
61 radeon_ring_write(ring, 0); in set_render_target()
62 radeon_ring_write(ring, cb_color_info); in set_render_target()
63 radeon_ring_write(ring, 0); in set_render_target()
64 radeon_ring_write(ring, (w - 1) | ((h - 1) << 16)); in set_render_target()
65 radeon_ring_write(ring, 0); in set_render_target()
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Dr600_blit_kms.c54 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in set_render_target()
55 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); in set_render_target()
56 radeon_ring_write(ring, gpu_addr >> 8); in set_render_target()
59 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); in set_render_target()
60 radeon_ring_write(ring, 2 << 0); in set_render_target()
63 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in set_render_target()
64 radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); in set_render_target()
65 radeon_ring_write(ring, (pitch << 0) | (slice << 10)); in set_render_target()
67 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in set_render_target()
68 radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); in set_render_target()
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Dr300.c183 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); in r300_fence_ring_emit()
184 radeon_ring_write(ring, 0); in r300_fence_ring_emit()
185 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); in r300_fence_ring_emit()
186 radeon_ring_write(ring, 0); in r300_fence_ring_emit()
188 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_fence_ring_emit()
189 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); in r300_fence_ring_emit()
190 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); in r300_fence_ring_emit()
191 radeon_ring_write(ring, R300_ZC_FLUSH); in r300_fence_ring_emit()
193 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_fence_ring_emit()
194 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | in r300_fence_ring_emit()
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Dni.c1160 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_fence_ring_emit()
1161 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in cayman_fence_ring_emit()
1162 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1163 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1164 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); in cayman_fence_ring_emit()
1165 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_fence_ring_emit()
1166 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1167 radeon_ring_write(ring, 10); /* poll interval */ in cayman_fence_ring_emit()
1169 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1170 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in cayman_fence_ring_emit()
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Drv515.c64 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
65 radeon_ring_write(ring, in rv515_ring_start()
70 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
71 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); in rv515_ring_start()
72 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
73 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); in rv515_ring_start()
74 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
75 radeon_ring_write(ring, 0); in rv515_ring_start()
76 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
77 radeon_ring_write(ring, 0); in rv515_ring_start()
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Dr200.c105 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
106 radeon_ring_write(ring, (1 << 16)); in r200_copy_dma()
113 radeon_ring_write(ring, PACKET0(0x720, 2)); in r200_copy_dma()
114 radeon_ring_write(ring, src_offset); in r200_copy_dma()
115 radeon_ring_write(ring, dst_offset); in r200_copy_dma()
116 radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); in r200_copy_dma()
120 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
121 radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE); in r200_copy_dma()
Dsi.c1909 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
1910 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_fence_ring_emit()
1911 radeon_ring_write(ring, 0); in si_fence_ring_emit()
1912 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
1913 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in si_fence_ring_emit()
1917 radeon_ring_write(ring, 0xFFFFFFFF); in si_fence_ring_emit()
1918 radeon_ring_write(ring, 0); in si_fence_ring_emit()
1919 radeon_ring_write(ring, 10); /* poll interval */ in si_fence_ring_emit()
1921 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
1922 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); in si_fence_ring_emit()
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Dr600.c1372 radeon_ring_write(ring, 0x80000000); in r600_gpu_is_lockup()
1373 radeon_ring_write(ring, 0x80000000); in r600_gpu_is_lockup()
2158 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2159 radeon_ring_write(ring, 0x1); in r600_cp_start()
2161 radeon_ring_write(ring, 0x0); in r600_cp_start()
2162 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2164 radeon_ring_write(ring, 0x3); in r600_cp_start()
2165 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2167 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in r600_cp_start()
2168 radeon_ring_write(ring, 0); in r600_cp_start()
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Dr420.c212 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); in r420_cp_errata_init()
213 radeon_ring_write(ring, rdev->config.r300.resync_scratch); in r420_cp_errata_init()
214 radeon_ring_write(ring, 0xDEADBEEF); in r420_cp_errata_init()
226 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r420_cp_errata_fini()
227 radeon_ring_write(ring, R300_RB3D_DC_FINISH); in r420_cp_errata_fini()
Devergreen.c1409 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in evergreen_ring_ib_execute()
1410 radeon_ring_write(ring, 1); in evergreen_ring_ib_execute()
1412 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in evergreen_ring_ib_execute()
1413 radeon_ring_write(ring, in evergreen_ring_ib_execute()
1418 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in evergreen_ring_ib_execute()
1419 radeon_ring_write(ring, ib->length_dw); in evergreen_ring_ib_execute()
1466 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in evergreen_cp_start()
1467 radeon_ring_write(ring, 0x1); in evergreen_cp_start()
1468 radeon_ring_write(ring, 0x0); in evergreen_cp_start()
1469 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); in evergreen_cp_start()
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Dr100.c854 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); in r100_fence_ring_emit()
855 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); in r100_fence_ring_emit()
856 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); in r100_fence_ring_emit()
857 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); in r100_fence_ring_emit()
859 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r100_fence_ring_emit()
860 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); in r100_fence_ring_emit()
861 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_fence_ring_emit()
862 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | in r100_fence_ring_emit()
864 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_fence_ring_emit()
865 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); in r100_fence_ring_emit()
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Dradeon_ring.c64 void radeon_ring_write(struct radeon_ring *ring, uint32_t v) in radeon_ring_write() function
356 radeon_ring_write(ring, ring->nop); in radeon_ring_commit()
Dradeon.h1697 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) in radeon_ring_write() function
1706 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);