/linux-3.4.99/arch/sh/lib64/ |
D | udivsi3.S | 17 mmulfx.w r21,r21,r19 20 mmulfx.w r25,r19,r19 23 msub.w r21,r19,r19 30 addi r19,-2,r21 32 mmulfx.w r19,r19,r19 36 mmacnfx.wl r25,r19,r21 40 mulu.l r25,r21,r19 43 shlrd r19,r0,r19 44 mulu.l r19,r22,r20 45 add r18,r19,r18 [all …]
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D | sdivsi3.S | 20 ldx.ub r20, r21, r19 /* u0.8 */ 23 muls.l r25, r19, r19 /* s2.38 */ 26 shari r19, 24, r19 /* truncate to s2.14 */ 27 sub r21, r19, r19 /* some 11 bit inverse in s1.14 */ 28 muls.l r19, r19, r21 /* u0.28 */ 32 shlli r19, 45, r19 /* multiply by two and convert to s2.58 */ 34 sub r19, r18, r18 39 shari r0, 16, r19 /* s-16.44 */ 40 muls.l r19, r18, r19 /* s-16.74 */ 43 shari r19, 30, r19 /* s-16.44 */ [all …]
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/linux-3.4.99/arch/ia64/kvm/ |
D | optvfault.S | 31 mov r19 = r25; \ 47 mov r25 = r19; \ 129 mov r19=ar.itc 132 add r19=r19,r18 135 st8 [r16] = r19 152 movl r19 = (KVM_VMM_BASE+(1<<KVM_VMM_SHIFT)) 159 ld8 r19=[r19] 162 add r19=r19,r18 166 st8 [r16] = r19 194 shr.u r26=r19,61 [all …]
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D | vmm_ivt.S | 75 mov r19=n;; \ 81 mov r19=n; /* prepare to save predicates */ \ 127 mov r19 = 1 152 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) 154 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits 156 or r19=r17,r19 // insert PTE control bits into r19 162 itc.i r19 // insert the TLB entry 174 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) 177 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits 179 or r19=r19,r17 // insert PTE control bits into r19 [all …]
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D | kvm_minstate.h | 212 .mem.offset 8,0; st8.spill [r3] = r19,16; \ 220 mov r19 = b7; \ 240 st8 [r25] = r19,16; /* b7 */ \ 248 adds r19 = PT(EML_UNAT)-PT(R4),r2; \ 250 st8 [r19] = r18; /* eml_unat */ \ 265 #define KVM_SAVE_MIN_WITH_COVER_R19 KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs, mov r15 = r19)
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/linux-3.4.99/arch/ia64/kernel/ |
D | ivt.S | 81 mov r19=n;; /* prepare to save predicates */ \ 119 mov r19=IA64_KR(PT_BASE) // get page table base address 137 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place 140 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir 146 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5 171 shr.u r19=r22,PAGE_SHIFT // shift pte index into position 174 dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr) 177 MOV_FROM_ISR(r19) // cr.isr bit 32 tells us if this is an insn miss 182 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss? 226 ld8 r19=[r28] // read *pud again [all …]
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D | fsys.S | 123 ld8 r19=[r17] // r19 = current->group_leader->real_parent 126 cmp.ne p6,p0=r18,r19 // did real_parent change? 127 mov r19=0 // i must not leak kernel bits... 135 mov r19=0 // i must not leak kernel bits... 252 add r19 = IA64_ITC_LASTCYCLE_OFFSET,r29 284 (p13) ld8 r25 = [r19] // get itc_lastcycle value 296 (p7) cmpxchg8.rel r3 = [r19],r2,ar.ccv 421 RSM_PSR_I(p0, r18, r19) // mask interrupt delivery 431 adds r19=1,r17 436 (p6) cmpxchg4.acq r9=[r31],r19,ar.ccv [all …]
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D | mca_asm.S | 68 ld4 r19=[r2],4 // r19=ptce_count[0] 80 cmp.ltu p6,p7=r24,r19 123 movl r19=PAGE_OFFSET 125 add r16=r19,r16 143 mov r19=1 // All MCA events are treated as monarch (for now) 174 mov r19=ip 177 dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT 196 mov r19=IA64_GRANULE_SHIFT<<2 198 mov cr.itir=r19 210 movl r19=PAGE_OFFSET [all …]
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D | gate.S | 199 .save ar.rnat, r19 200 mov r19=ar.rnat // save RNaT before switching backing store area 208 st8 [r14]=r19 // save sc_ar_rnat 222 (p8) st8 [r18]=r19 // if bspstore points at RNaT slot, store RNaT there now 333 mov r19=NR_syscalls-1 // A 338 cmp.geu p6,p7=r19,r17 // A (sysnr > 0 && sysnr < 1024+NR_syscalls)?
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D | relocate_kernel.S | 70 ld4 r19=[r2],4 // r19=ptce_count[0] 81 cmp.ltu p6,p7=r24,r19 120 movl r19=PAGE_OFFSET 122 add r16=r19,r16 274 st8 [in0]=r19, 8 // r19
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D | esi_stub.S | 83 .ret0: mov loc5=r19 // old ar.bsp 88 mov r19=loc5 // save virtual mode bspstore
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D | efi_stub.S | 73 mov loc5=r19 78 mov r19=loc5
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D | entry.S | 293 mov.m r19=ar.rnat 355 st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat 401 ld8 r19=[r15],24 // restore fpsr 459 mov ar.fpsr=r19 // restore fpsr 724 MOV_FROM_ITC(pUStk, p9, r22, r19) // fetch time at leave 728 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs" 737 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs" 808 shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition 812 mov r19=ar.bsp // M2 get new backing store pointer 820 mov r19=ar.bsp // M2 get new backing store pointer [all …]
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D | head.S | 335 mov r19=IA64_TR_CURRENT_STACK 337 itr.d dtr[r19]=r18 361 movl r19=__phys_per_cpu_start 365 add r19=r19,r18 373 ld8 r21=[r19],8;; 378 mov r19=r20 382 tpa r19=r19 385 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0 467 add r19=IA64_NUM_DBG_REGS*8,in0 478 st8.nta [r19]=r17,8 [all …]
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/linux-3.4.99/arch/unicore32/lib/ |
D | copy_page.S | 27 stm.w (r17 - r19, lr), [sp-] 30 mov r19, #COPY_COUNT 36 sub.a r19, r19, #1 38 ldm.w (r17 - r19, pc), [sp]+
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/linux-3.4.99/arch/parisc/kernel/ |
D | syscall.S | 137 STREG %r19, TASK_PT_GR19(%r1) 141 extrd,u %r2,63,1,%r19 /* W hidden in bottom bit */ 143 xor %r19,%r2,%r2 /* clear bottom bit */ 144 depd,z %r19,1,1,%r19 145 std %r19,TASK_PT_PSW(%r1) 173 copy %r19,%r2 /* W bit back to r2 */ 194 ldo R%sys_call_table(%r1), %r19 196 ldo R%sys_call_table64(%r1), %r19 199 ldo R%sys_call_table(%r1), %r19 204 LDREGX %r20(%r19), %r19 [all …]
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D | pacache.S | 57 rsm PSW_SM_I, %r19 /* save I-bit state */ 183 or %r1, %r19, %r1 /* I-bit to state on entry */ 291 ldd 0(%r25), %r19 303 std %r19, 0(%r26) 306 ldd 32(%r25), %r19 313 std %r19, 32(%r26) 316 ldd 64(%r25), %r19 323 std %r19, 64(%r26) 326 ldd 96(%r25), %r19 333 std %r19, 96(%r26) [all …]
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D | entry.S | 874 LDREG PT_IAOQ0(%r16),%r19 875 depi 3,31,2,%r19 876 STREG %r19,PT_IAOQ0(%r16) 877 LDREG PT_IAOQ1(%r16),%r19 878 depi 3,31,2,%r19 879 STREG %r19,PT_IAOQ1(%r16) 880 LDREG PT_PSW(%r16),%r19 886 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */ 888 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */ 889 STREG %r19,PT_PSW(%r16) [all …]
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/linux-3.4.99/arch/powerpc/kvm/ |
D | booke_interrupts.S | 142 stw r19, VCPU_GPR(r19)(r4) 226 lwz r19, VCPU_GPR(r19)(r4) 264 stw r19, VCPU_GPR(r19)(r4) 284 lwz r19, HOST_NV_GPR(r19)(r1) 329 stw r19, HOST_NV_GPR(r19)(r1) 349 lwz r19, VCPU_GPR(r19)(r4)
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D | book3s_interrupts.S | 47 PPC_LL r19, VCPU_GPR(r19)(vcpu); \ 139 PPC_STL r19, VCPU_GPR(r19)(r7)
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/linux-3.4.99/arch/alpha/kernel/ |
D | signal.c | 204 err |= __get_user(regs->r19, sc->sc_regs+19); in restore_sigcontext() 343 err |= __put_user(regs->r19, sc->sc_regs+19); in setup_sigcontext() 506 syscall_restart(unsigned long r0, unsigned long r19, in syscall_restart() argument 519 regs->r19 = r19; in syscall_restart() 544 unsigned long r0, unsigned long r19) in do_signal() argument 566 syscall_restart(r0, r19, regs, &ka); in do_signal() 587 regs->r19 = r19; in do_signal() 611 unsigned long r0, unsigned long r19) in do_notify_resume() argument 614 do_signal(regs, sw, r0, r19); in do_notify_resume()
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/linux-3.4.99/arch/microblaze/kernel/ |
D | entry-nommu.S | 87 swi r19, r1, PT_R19 128 lwi r19, r6, TI_FLAGS /* get flags in thread info */ 131 andi r11, r19, _TIF_NEED_RESCHED 135 1: andi r11, r19, _TIF_SIGPENDING 175 lwi r19, r1, PT_R19 239 swi r19, r1, PT_R19 329 swi r19, r1, PT_R19 402 swi r19, r11, CC_R19 452 lwi r19, r11, CC_R19 481 andi r11, r19, _TIF_NEED_RESCHED [all …]
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/linux-3.4.99/arch/microblaze/lib/ |
D | uaccess_old.S | 109 2: lwi r19, r6, 0x0004 + offset; \ 117 10: swi r19, r5, 0x0004 + offset; \ 197 swi r19, r1, 12 220 lwi r19, r1, 12 240 lwi r19, r1, 12
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/linux-3.4.99/arch/parisc/hpux/ |
D | gate.S | 30 ldw -60(%r30), %r19 ;! 7th argument 64 STREG %r19, TASK_PT_GR19(%r1) /* 7th argument */ 88 stw %r19, -60(%r30) ;! 7th argument
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/linux-3.4.99/arch/ia64/lib/ |
D | xor.S | 117 mov r19 = in4 126 (p[0]) ld8.nta s4[0] = [r19], 8 160 mov r19 = in4 170 (p[0]) ld8.nta s4[0] = [r19], 8
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