| /linux-3.4.99/drivers/gpu/drm/nouveau/ |
| D | nouveau_perf.c | 242 sprintf(pm->perflvl[0].name, "performance_level_0"); in legacy_perf_init()
243 pm->perflvl[0].memory = ROM16(entry[0]) * 20; in legacy_perf_init()
248 nouveau_perf_voltage(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nouveau_perf_voltage() argument
255 id = perflvl->volt_min; in nouveau_perf_voltage()
256 perflvl->volt_min = 0; in nouveau_perf_voltage()
262 perflvl->volt_min = id * 10000; in nouveau_perf_voltage()
263 perflvl->volt_max = perflvl->volt_min; in nouveau_perf_voltage()
284 perflvl->volt_min = ROM32(vmap[0]); in nouveau_perf_voltage()
285 perflvl->volt_max = ROM32(vmap[4]); in nouveau_perf_voltage()
308 struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl]; in nouveau_perf_init() local
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| D | nouveau_pm.c | 102 nouveau_pm_perflvl_aux(struct drm_device *dev, struct nouveau_pm_level *perflvl, in nouveau_pm_perflvl_aux() argument
114 ret = nouveau_pwmfan_set(dev, perflvl->fanspeed); in nouveau_pm_perflvl_aux()
122 if (perflvl->volt_min && b->volt_min > a->volt_min) { in nouveau_pm_perflvl_aux()
123 ret = pm->voltage_set(dev, perflvl->volt_min); in nouveau_pm_perflvl_aux()
135 nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nouveau_pm_perflvl_set() argument
142 if (perflvl == pm->cur) in nouveau_pm_perflvl_set()
145 ret = nouveau_pm_perflvl_aux(dev, perflvl, pm->cur, perflvl); in nouveau_pm_perflvl_set()
149 state = pm->clocks_pre(dev, perflvl); in nouveau_pm_perflvl_set()
158 ret = nouveau_pm_perflvl_aux(dev, perflvl, perflvl, pm->cur); in nouveau_pm_perflvl_set()
162 pm->cur = perflvl; in nouveau_pm_perflvl_set()
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| D | nvc0_pm.c | 142 nvc0_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nvc0_pm_clocks_get() argument
144 perflvl->shader = read_clk(dev, 0x00); in nvc0_pm_clocks_get()
145 perflvl->core = perflvl->shader / 2; in nvc0_pm_clocks_get()
146 perflvl->memory = read_mem(dev); in nvc0_pm_clocks_get()
147 perflvl->rop = read_clk(dev, 0x01); in nvc0_pm_clocks_get()
148 perflvl->hub07 = read_clk(dev, 0x02); in nvc0_pm_clocks_get()
149 perflvl->hub06 = read_clk(dev, 0x07); in nvc0_pm_clocks_get()
150 perflvl->hub01 = read_clk(dev, 0x08); in nvc0_pm_clocks_get()
151 perflvl->copy = read_clk(dev, 0x09); in nvc0_pm_clocks_get()
152 perflvl->daemon = read_clk(dev, 0x0c); in nvc0_pm_clocks_get()
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| D | nv50_pm.c | 337 nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nv50_pm_clocks_get() argument
344 perflvl->core = read_clk(dev, clk_src_nvclk); in nv50_pm_clocks_get()
345 perflvl->shader = read_clk(dev, clk_src_sclk); in nv50_pm_clocks_get()
346 perflvl->memory = read_clk(dev, clk_src_mclk); in nv50_pm_clocks_get()
348 perflvl->vdec = read_clk(dev, clk_src_vdec); in nv50_pm_clocks_get()
349 perflvl->dom6 = read_clk(dev, clk_src_dom6); in nv50_pm_clocks_get()
356 struct nouveau_pm_level *perflvl; member
513 struct nouveau_pm_level *perflvl = info->perflvl; in mclk_timing_set() local
520 if (val != perflvl->timing.reg[i]) in mclk_timing_set()
521 hwsq_wr32(hwsq, reg, perflvl->timing.reg[i]); in mclk_timing_set()
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| D | nva3_pm.c | 220 nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nva3_pm_clocks_get() argument
222 perflvl->core = read_pll(dev, 0x00, 0x4200); in nva3_pm_clocks_get()
223 perflvl->shader = read_pll(dev, 0x01, 0x4220); in nva3_pm_clocks_get()
224 perflvl->memory = read_pll(dev, 0x02, 0x4000); in nva3_pm_clocks_get()
225 perflvl->unka0 = read_clk(dev, 0x20, false); in nva3_pm_clocks_get()
226 perflvl->vdec = read_clk(dev, 0x21, false); in nva3_pm_clocks_get()
227 perflvl->daemon = read_clk(dev, 0x25, false); in nva3_pm_clocks_get()
228 perflvl->copy = perflvl->core; in nva3_pm_clocks_get()
241 nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nva3_pm_clocks_pre() argument
250 ret = calc_clk(dev, 0x10, 0x4200, perflvl->core, &info->nclk); in nva3_pm_clocks_pre()
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| D | nv04_pm.c | 31 nv04_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nv04_pm_clocks_get() argument
38 perflvl->core = ret; in nv04_pm_clocks_get()
43 perflvl->memory = ret; in nv04_pm_clocks_get()
75 nv04_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nv04_pm_clocks_pre() argument
84 ret = calc_pll(dev, PLL_CORE, perflvl->core, &info->core); in nv04_pm_clocks_pre()
88 if (perflvl->memory) { in nv04_pm_clocks_pre()
89 ret = calc_pll(dev, PLL_MEMORY, perflvl->memory, &info->memory); in nv04_pm_clocks_pre()
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| D | nv40_pm.c | 89 nv40_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nv40_pm_clocks_get() argument
93 perflvl->core = read_clk(dev, (ctrl & 0x00000003) >> 0); in nv40_pm_clocks_get()
94 perflvl->shader = read_clk(dev, (ctrl & 0x00000030) >> 4); in nv40_pm_clocks_get()
95 perflvl->memory = read_pll_2(dev, 0x4020); in nv40_pm_clocks_get()
142 nv40_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) in nv40_pm_clocks_pre() argument
154 ret = nv40_calc_pll(dev, 0x004000, &pll, perflvl->core, in nv40_pm_clocks_pre()
168 if (perflvl->shader && perflvl->shader != perflvl->core) { in nv40_pm_clocks_pre()
169 ret = nv40_calc_pll(dev, 0x004008, &pll, perflvl->shader, in nv40_pm_clocks_pre()
182 if (!perflvl->memory) { in nv40_pm_clocks_pre()
187 ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory, in nv40_pm_clocks_pre()
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| D | nouveau_drv.c | 115 MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
117 module_param_named(perflvl, nouveau_perflvl, charp, 0400);
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| D | nouveau_mem.c | 965 struct nouveau_pm_level *perflvl) in nouveau_mem_exec() argument
968 struct nouveau_pm_memtiming *info = &perflvl->timing; in nouveau_mem_exec()
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| D | nouveau_drv.h | 555 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; member
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