| /linux-3.4.99/drivers/video/nvidia/ |
| D | nv_setup.c | 60 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value) in NVWriteCrtc() argument
62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVWriteCrtc()
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); in NVWriteCrtc()
65 u8 NVReadCrtc(struct nvidia_par *par, u8 index) in NVReadCrtc() argument
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVReadCrtc()
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); in NVReadCrtc()
70 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value) in NVWriteGr() argument
72 VGA_WR08(par->PVIO, VGA_GFX_I, index); in NVWriteGr()
73 VGA_WR08(par->PVIO, VGA_GFX_D, value); in NVWriteGr()
75 u8 NVReadGr(struct nvidia_par *par, u8 index) in NVReadGr() argument
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| D | nv_hw.c | 57 void NVLockUnlock(struct nvidia_par *par, int Lock) in NVLockUnlock() argument
61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
73 int NVShowHideCursor(struct nvidia_par *par, int ShowHide) in NVShowHideCursor() argument
75 int cur = par->CurrentState->cursor1; in NVShowHideCursor()
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | in NVShowHideCursor()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
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| D | nv_accel.c | 74 struct nvidia_par *par = info->par; in nvidiafb_safe_mode() local
78 par->lockup = 1; in nvidiafb_safe_mode()
83 struct nvidia_par *par = info->par; in NVFlush() local
86 while (--count && READ_GET(par) != par->dmaPut) ; in NVFlush()
96 struct nvidia_par *par = info->par; in NVSync() local
99 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ; in NVSync()
107 static void NVDmaKickoff(struct nvidia_par *par) in NVDmaKickoff() argument
109 if (par->dmaCurrent != par->dmaPut) { in NVDmaKickoff()
110 par->dmaPut = par->dmaCurrent; in NVDmaKickoff()
111 WRITE_PUT(par, par->dmaPut); in NVDmaKickoff()
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| D | nv_i2c.c | 31 struct nvidia_par *par = chan->par; in nvidia_gpio_setscl() local
34 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setscl()
41 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setscl()
47 struct nvidia_par *par = chan->par; in nvidia_gpio_setsda() local
50 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setsda()
57 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setsda()
63 struct nvidia_par *par = chan->par; in nvidia_gpio_getscl() local
66 if (NVReadCrtc(par, chan->ddc_base) & 0x04) in nvidia_gpio_getscl()
75 struct nvidia_par *par = chan->par; in nvidia_gpio_getsda() local
78 if (NVReadCrtc(par, chan->ddc_base) & 0x08) in nvidia_gpio_getsda()
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| D | nvidia.c | 123 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8, in nvidiafb_load_cursor_image() argument
149 NV_WR32(&par->CURSOR[k++], 0, tmp); in nvidiafb_load_cursor_image()
155 static void nvidia_write_clut(struct nvidia_par *par, in nvidia_write_clut() argument
158 NVWriteDacMask(par, 0xff); in nvidia_write_clut()
159 NVWriteDacWriteAddr(par, regnum); in nvidia_write_clut()
160 NVWriteDacData(par, red); in nvidia_write_clut()
161 NVWriteDacData(par, green); in nvidia_write_clut()
162 NVWriteDacData(par, blue); in nvidia_write_clut()
165 static void nvidia_read_clut(struct nvidia_par *par, in nvidia_read_clut() argument
168 NVWriteDacMask(par, 0xff); in nvidia_read_clut()
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| /linux-3.4.99/drivers/video/savage/ |
| D | savagefb_driver.c | 85 static void vgaHWSeqReset(struct savagefb_par *par, int start) in vgaHWSeqReset() argument
88 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */ in vgaHWSeqReset()
90 VGAwSEQ(0x00, 0x03, par); /* End Reset */ in vgaHWSeqReset()
93 static void vgaHWProtect(struct savagefb_par *par, int on) in vgaHWProtect() argument
101 tmp = VGArSEQ(0x01, par); in vgaHWProtect()
103 vgaHWSeqReset(par, 1); /* start synchronous reset */ in vgaHWProtect()
104 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */ in vgaHWProtect()
106 VGAenablePalette(par); in vgaHWProtect()
112 tmp = VGArSEQ(0x01, par); in vgaHWProtect()
114 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */ in vgaHWProtect()
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| /linux-3.4.99/drivers/video/geode/ |
| D | suspend_gx.c | 20 static void gx_save_regs(struct gxfb_par *par) in gx_save_regs() argument
26 i = read_gp(par, GP_BLT_STATUS); in gx_save_regs()
30 rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); in gx_save_regs()
31 rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); in gx_save_regs()
33 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); in gx_save_regs()
36 memcpy(par->gp, par->gp_regs, sizeof(par->gp)); in gx_save_regs()
37 memcpy(par->dc, par->dc_regs, sizeof(par->dc)); in gx_save_regs()
38 memcpy(par->vp, par->vid_regs, sizeof(par->vp)); in gx_save_regs()
39 memcpy(par->fp, par->vid_regs + VP_FP_START, sizeof(par->fp)); in gx_save_regs()
42 write_dc(par, DC_PAL_ADDRESS, 0); in gx_save_regs()
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| D | lxfb_ops.c | 186 struct lxfb_par *par = info->par; in lx_graphics_disable() local
191 write_vp(par, VP_A1T, 0); in lx_graphics_disable()
192 write_vp(par, VP_A2T, 0); in lx_graphics_disable()
193 write_vp(par, VP_A3T, 0); in lx_graphics_disable()
196 val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE | in lx_graphics_disable()
199 write_dc(par, DC_GENERAL_CFG, val); in lx_graphics_disable()
201 val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN; in lx_graphics_disable()
202 write_vp(par, VP_VCFG, val); in lx_graphics_disable()
204 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK | in lx_graphics_disable()
207 val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN; in lx_graphics_disable()
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| /linux-3.4.99/drivers/video/ |
| D | broadsheetfb.c | 119 static void broadsheet_gpio_issue_data(struct broadsheetfb_par *par, u16 data) in broadsheet_gpio_issue_data() argument
121 par->board->set_ctl(par, BS_WR, 0); in broadsheet_gpio_issue_data()
122 par->board->set_hdb(par, data); in broadsheet_gpio_issue_data()
123 par->board->set_ctl(par, BS_WR, 1); in broadsheet_gpio_issue_data()
126 static void broadsheet_gpio_issue_cmd(struct broadsheetfb_par *par, u16 data) in broadsheet_gpio_issue_cmd() argument
128 par->board->set_ctl(par, BS_DC, 0); in broadsheet_gpio_issue_cmd()
129 broadsheet_gpio_issue_data(par, data); in broadsheet_gpio_issue_cmd()
132 static void broadsheet_gpio_send_command(struct broadsheetfb_par *par, u16 data) in broadsheet_gpio_send_command() argument
134 par->board->wait_for_rdy(par); in broadsheet_gpio_send_command()
136 par->board->set_ctl(par, BS_CS, 0); in broadsheet_gpio_send_command()
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| D | i740fb.c | 103 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val) in i740outb() argument
105 vga_mm_w(par->regs, port, val); in i740outb()
107 static inline u8 i740inb(struct i740fb_par *par, u16 port) in i740inb() argument
109 return vga_mm_r(par->regs, port); in i740inb()
111 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val) in i740outreg() argument
113 vga_mm_w_fast(par->regs, port, reg, val); in i740outreg()
115 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg) in i740inreg() argument
117 vga_mm_w(par->regs, port, reg); in i740inreg()
118 return vga_mm_r(par->regs, port+1); in i740inreg()
120 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg, in i740outreg_mask() argument
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| D | s3fb.c | 201 static u8 s3fb_ddc_read(struct s3fb_info *par) in s3fb_ddc_read() argument
203 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_read()
204 return readb(par->mmio + DDC_MMIO_REG); in s3fb_ddc_read()
206 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
209 static void s3fb_ddc_write(struct s3fb_info *par, u8 val) in s3fb_ddc_write() argument
211 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_write()
212 writeb(val, par->mmio + DDC_MMIO_REG); in s3fb_ddc_write()
214 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
219 struct s3fb_info *par = data; in s3fb_ddc_setscl() local
222 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; in s3fb_ddc_setscl()
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| D | tridentfb.c | 36 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
38 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
40 (struct tridentfb_par *par, const char*,
167 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) in writemmr() argument
169 fb_writel(v, par->io_virt + r); in writemmr()
172 static inline u32 readmmr(struct tridentfb_par *par, u16 r) in readmmr() argument
174 return fb_readl(par->io_virt + r); in readmmr()
183 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) in blade_init_accel() argument
189 writemmr(par, 0x21C0, v2); in blade_init_accel()
190 writemmr(par, 0x21C4, v2); in blade_init_accel()
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| D | pm3fb.c | 101 static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off) in PM3_READ_REG() argument
103 return fb_readl(par->v_regs + off); in PM3_READ_REG()
106 static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v) in PM3_WRITE_REG() argument
108 fb_writel(v, par->v_regs + off); in PM3_WRITE_REG()
111 static inline void PM3_WAIT(struct pm3_par *par, u32 n) in PM3_WAIT() argument
113 while (PM3_READ_REG(par, PM3InFIFOSpace) < n) in PM3_WAIT()
117 static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v) in PM3_WRITE_DAC_REG() argument
119 PM3_WAIT(par, 3); in PM3_WRITE_DAC_REG()
120 PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff); in PM3_WRITE_DAC_REG()
121 PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff); in PM3_WRITE_DAC_REG()
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| D | pmagb-b-fb.c | 69 static inline void sfb_write(struct pmagbbfb_par *par, unsigned int reg, u32 v) in sfb_write() argument
71 writel(v, par->sfb + reg / 4); in sfb_write()
74 static inline u32 sfb_read(struct pmagbbfb_par *par, unsigned int reg) in sfb_read() argument
76 return readl(par->sfb + reg / 4); in sfb_read()
79 static inline void dac_write(struct pmagbbfb_par *par, unsigned int reg, u8 v) in dac_write() argument
81 writeb(v, par->dac + reg / 4); in dac_write()
84 static inline u8 dac_read(struct pmagbbfb_par *par, unsigned int reg) in dac_read() argument
86 return readb(par->dac + reg / 4); in dac_read()
89 static inline void gp0_write(struct pmagbbfb_par *par, u32 v) in gp0_write() argument
91 writel(v, par->mmio + PMAGB_B_GP0); in gp0_write()
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| D | neofb.c | 150 static inline void write_le32(int regindex, u32 val, const struct neofb_par *par) in write_le32() argument
152 writel(val, par->neo2200 + par->cursorOff + regindex); in write_le32()
208 struct neofb_par *par, long freq) in neoCalcVCLK() argument
238 par->VCLK3NumeratorLow = n_best; in neoCalcVCLK()
239 par->VCLK3NumeratorHigh = (f_best << 7); in neoCalcVCLK()
241 par->VCLK3NumeratorLow = n_best | (f_best << 7); in neoCalcVCLK()
243 par->VCLK3Denominator = d_best; in neoCalcVCLK()
248 par->VCLK3NumeratorLow, in neoCalcVCLK()
249 par->VCLK3NumeratorHigh, in neoCalcVCLK()
250 par->VCLK3Denominator, f_best_diff); in neoCalcVCLK()
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| D | imsttfb.c | 426 getclkMHz(struct imstt_par *par) in getclkMHz() argument
430 clk_m = par->init.pclk_m; in getclkMHz()
431 clk_n = par->init.pclk_n; in getclkMHz()
432 clk_p = par->init.pclk_p; in getclkMHz()
438 setclkMHz(struct imstt_par *par, __u32 MHz) in setclkMHz() argument
464 par->init.pclk_m = clk_m; in setclkMHz()
465 par->init.pclk_n = clk_n; in setclkMHz()
466 par->init.pclk_p = 0; in setclkMHz()
470 compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres) in compute_imstt_regvals_ibm() argument
472 struct imstt_regvals *init = &par->init; in compute_imstt_regvals_ibm()
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| D | carminefb.c | 138 static void c_set_disp_reg(const struct carmine_fb *par, in c_set_disp_reg() argument
141 writel(val, par->display_reg + offset); in c_set_disp_reg()
144 static u32 c_get_disp_reg(const struct carmine_fb *par, in c_get_disp_reg() argument
147 return readl(par->display_reg + offset); in c_get_disp_reg()
219 static void carmine_init_display_param(struct carmine_fb *par) in carmine_init_display_param() argument
225 u32 soffset = par->smem_offset; in carmine_init_display_param()
227 c_set_disp_reg(par, CARMINE_DISP_REG_C_TRANS, 0); in carmine_init_display_param()
228 c_set_disp_reg(par, CARMINE_DISP_REG_MLMR_TRANS, 0); in carmine_init_display_param()
229 c_set_disp_reg(par, CARMINE_DISP_REG_CURSOR_MODE, in carmine_init_display_param()
235 c_set_disp_reg(par, CARMINE_DISP_REG_CUR1_POS, 0 << 16 | 0); in carmine_init_display_param()
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| /linux-3.4.99/drivers/video/riva/ |
| D | nv_driver.c | 46 static inline unsigned char MISCin(struct riva_par *par) in MISCin() argument
48 return (VGA_RD08(par->riva.PVIO, 0x3cc)); in MISCin()
52 riva_is_connected(struct riva_par *par, Bool second) in riva_is_connected() argument
54 volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0; in riva_is_connected()
69 NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140); in riva_is_connected()
70 NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000); in riva_is_connected()
76 NV_WR32(par->riva.PRAMDAC0, 0x0608, in riva_is_connected()
77 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF); in riva_is_connected()
86 riva_override_CRTC(struct riva_par *par) in riva_override_CRTC() argument
90 par->SecondCRTC ? 1 : 0); in riva_override_CRTC()
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| D | rivafb-i2c.c | 30 struct riva_par *par = chan->par; in riva_gpio_setscl() local
33 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
34 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; in riva_gpio_setscl()
41 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
42 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); in riva_gpio_setscl()
48 struct riva_par *par = chan->par; in riva_gpio_setsda() local
51 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setsda()
52 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; in riva_gpio_setsda()
59 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setsda()
60 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); in riva_gpio_setsda()
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| /linux-3.4.99/drivers/video/aty/ |
| D | mach64_accel.c | 39 void aty_reset_engine(const struct atyfb_par *par) in aty_reset_engine() argument
43 aty_ld_le32(GEN_TEST_CNTL, par) & in aty_reset_engine()
44 ~(GUI_ENGINE_ENABLE | HWCURSOR_ENABLE), par); in aty_reset_engine()
47 aty_ld_le32(GEN_TEST_CNTL, par) | GUI_ENGINE_ENABLE, par); in aty_reset_engine()
51 aty_ld_le32(BUS_CNTL, par) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK, par); in aty_reset_engine()
54 static void reset_GTC_3D_engine(const struct atyfb_par *par) in reset_GTC_3D_engine() argument
56 aty_st_le32(SCALE_3D_CNTL, 0xc0, par); in reset_GTC_3D_engine()
58 aty_st_le32(SETUP_CNTL, 0x00, par); in reset_GTC_3D_engine()
60 aty_st_le32(SCALE_3D_CNTL, 0x00, par); in reset_GTC_3D_engine()
64 void aty_init_engine(struct atyfb_par *par, struct fb_info *info) in aty_init_engine() argument
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| D | atyfb_base.c | 151 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par) in aty_st_lcd() argument
154 aty_st_le32(lt_lcd_regs[index], val, par); in aty_st_lcd()
159 temp = aty_ld_le32(LCD_INDEX, par); in aty_st_lcd()
160 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par); in aty_st_lcd()
162 aty_st_le32(LCD_DATA, val, par); in aty_st_lcd()
166 u32 aty_ld_lcd(int index, const struct atyfb_par *par) in aty_ld_lcd() argument
169 return aty_ld_le32(lt_lcd_regs[index], par); in aty_ld_lcd()
174 temp = aty_ld_le32(LCD_INDEX, par); in aty_ld_lcd()
175 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par); in aty_ld_lcd()
177 return aty_ld_le32(LCD_DATA, par); in aty_ld_lcd()
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| D | mach64_gx.c | 42 static void aty_dac_waste4(const struct atyfb_par *par) in aty_dac_waste4() argument
44 (void) aty_ld_8(DAC_REGS, par); in aty_dac_waste4()
46 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
47 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
48 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
49 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
52 static void aty_StrobeClock(const struct atyfb_par *par) in aty_StrobeClock() argument
58 tmp = aty_ld_8(CLOCK_CNTL, par); in aty_StrobeClock()
59 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par); in aty_StrobeClock()
68 static void aty_st_514(int offset, u8 val, const struct atyfb_par *par) in aty_st_514() argument
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| /linux-3.4.99/drivers/video/mb862xx/ |
| D | mb862xxfbdrv.c | 85 struct mb862xxfb_par *par = info->par; in mb862xxfb_setcolreg() local
94 par->pseudo_palette[regno] = val; in mb862xxfb_setcolreg()
206 struct mb862xxfb_par *par = fbi->par; in mb862xxfb_set_par() local
209 dev_dbg(par->dev, "%s\n", __func__); in mb862xxfb_set_par()
210 if (par->type == BT_CORALP) in mb862xxfb_set_par()
213 if (par->pre_init) in mb862xxfb_set_par()
222 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1; in mb862xxfb_set_par()
227 dev_dbg(par->dev, "SC 0x%lx\n", sc); in mb862xxfb_set_par()
276 struct mb862xxfb_par *par = info->par; in mb862xxfb_pan() local
289 struct mb862xxfb_par *par = fbi->par; in mb862xxfb_blank() local
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| /linux-3.4.99/drivers/video/i810/ |
| D | i810-i2c.c | 45 struct i810fb_par *par = chan->par; in i810i2c_setscl() local
46 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setscl()
58 struct i810fb_par *par = chan->par; in i810i2c_setsda() local
59 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setsda()
71 struct i810fb_par *par = chan->par; in i810i2c_getscl() local
72 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_getscl()
82 struct i810fb_par *par = chan->par; in i810i2c_getsda() local
83 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_getsda()
97 chan->adapter.dev.parent = &chan->par->dev->dev; in i810_setup_i2c_bus()
116 dev_dbg(&chan->par->dev->dev, "I2C bus %s registered.\n",name); in i810_setup_i2c_bus()
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| D | i810_main.c | 97 static void i810fb_release_resource (struct fb_info *info, struct i810fb_par *par);
229 static void i810_load_pll(struct i810fb_par *par) in i810_load_pll() argument
232 u8 __iomem *mmio = par->mmio_start_virtual; in i810_load_pll()
234 tmp1 = par->regs.M | par->regs.N << 16; in i810_load_pll()
239 tmp1 = par->regs.P; in i810_load_pll()
244 i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1); in i810_load_pll()
255 static void i810_load_vga(struct i810fb_par *par) in i810_load_vga() argument
257 u8 __iomem *mmio = par->mmio_start_virtual; in i810_load_vga()
261 i810_writeb(CR_DATA_CGA, mmio, par->interlace); in i810_load_vga()
264 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00); in i810_load_vga()
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