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Searched refs:nv_ro32 (Results 1 – 10 of 10) sorted by relevance

/linux-3.4.99/drivers/gpu/drm/nouveau/
Dnv50_fifo.c358 nv_wr32(dev, 0x3330, nv_ro32(ramfc, 0x00)); in nv50_fifo_load_context()
359 nv_wr32(dev, 0x3334, nv_ro32(ramfc, 0x04)); in nv50_fifo_load_context()
360 nv_wr32(dev, 0x3240, nv_ro32(ramfc, 0x08)); in nv50_fifo_load_context()
361 nv_wr32(dev, 0x3320, nv_ro32(ramfc, 0x0c)); in nv50_fifo_load_context()
362 nv_wr32(dev, 0x3244, nv_ro32(ramfc, 0x10)); in nv50_fifo_load_context()
363 nv_wr32(dev, 0x3328, nv_ro32(ramfc, 0x14)); in nv50_fifo_load_context()
364 nv_wr32(dev, 0x3368, nv_ro32(ramfc, 0x18)); in nv50_fifo_load_context()
365 nv_wr32(dev, 0x336c, nv_ro32(ramfc, 0x1c)); in nv50_fifo_load_context()
366 nv_wr32(dev, 0x3370, nv_ro32(ramfc, 0x20)); in nv50_fifo_load_context()
367 nv_wr32(dev, 0x3374, nv_ro32(ramfc, 0x24)); in nv50_fifo_load_context()
[all …]
Dnouveau_ramht.c59 u32 ctx = nv_ro32(ramht, offset + 4); in nouveau_ramht_entry_valid()
71 u32 ctx = nv_ro32(ramht, offset + 4); in nouveau_ramht_entry_same_channel()
144 chan->id, co, nv_ro32(ramht, co)); in nouveau_ramht_insert()
198 (handle == nv_ro32(ramht, co))) { in nouveau_ramht_remove_hash()
201 chan->id, co, handle, nv_ro32(ramht, co + 4)); in nouveau_ramht_remove_hash()
Dnouveau_sgdma.c167 tmp[0] = nv_ro32(pgt, base + 0x0); in nv44_sgdma_fill()
168 tmp[1] = nv_ro32(pgt, base + 0x4); in nv44_sgdma_fill()
169 tmp[2] = nv_ro32(pgt, base + 0x8); in nv44_sgdma_fill()
170 tmp[3] = nv_ro32(pgt, base + 0xc); in nv44_sgdma_fill()
442 return (nv_ro32(gpuobj, 4 * pte) & ~NV_CTXDMA_PAGE_MASK) | in nouveau_sgdma_get_physical()
Dnv50_instmem.c187 tmp = nv_ro32(chan->ramin, 0); in nv50_instmem_init()
189 if (nv_ro32(chan->ramin, 0) != ~tmp) { in nv50_instmem_init()
Dnouveau_object.c922 gpuobj->suspend[i/4] = nv_ro32(gpuobj, i); in nouveau_gpuobj_suspend()
999 nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset) in nv_ro32() function
Dnv04_fifo.c44 #define RAMFC_RD(offset) nv_ro32(chan->ramfc, NV04_RAMFC_##offset)
Dnvc0_graph.c144 ctx[i / 4] = nv_ro32(grch->grctx, i); in nvc0_graph_construct_context()
Dnv50_display.c155 if (nv_ro32(disp->ntfy, 0x000)) in nv50_display_sync()
Dnvc0_grctx.c1820 u32 reg = nv_ro32(grch->mmio, i + 0); in nvc0_grctx_generate()
1821 nv_wr32(dev, reg, nv_ro32(grch->mmio, i + 4)); in nvc0_grctx_generate()
Dnouveau_drv.h1623 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);