1 /* 2 * Copyright 2007-2010 Analog Devices Inc. 3 * 4 * Licensed under the ADI BSD license or the GPL-2 (or later) 5 */ 6 7 #ifndef _DEF_BF525_H 8 #define _DEF_BF525_H 9 10 /* BF525 is BF522 + USB */ 11 #include "defBF522.h" 12 13 /* USB Control Registers */ 14 15 #define USB_FADDR 0xffc03800 /* Function address register */ 16 #define USB_POWER 0xffc03804 /* Power management register */ 17 #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ 18 #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ 19 #define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ 20 #define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ 21 #define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ 22 #define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ 23 #define USB_FRAME 0xffc03820 /* USB frame number */ 24 #define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ 25 #define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ 26 #define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ 27 #define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ 28 29 /* USB Packet Control Registers */ 30 31 #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ 32 #define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ 33 #define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ 34 #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ 35 #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ 36 #define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ 37 #define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ 38 #define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ 39 #define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ 40 #define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ 41 #define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ 42 #define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ 43 #define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ 44 45 /* USB Endpoint FIFO Registers */ 46 47 #define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ 48 #define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ 49 #define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ 50 #define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ 51 #define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ 52 #define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ 53 #define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ 54 #define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ 55 56 /* USB OTG Control Registers */ 57 58 #define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ 59 #define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ 60 #define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ 61 62 /* USB Phy Control Registers */ 63 64 #define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ 65 #define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ 66 #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ 67 #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ 68 #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ 69 70 /* (APHY_CNTRL is for ADI usage only) */ 71 72 #define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ 73 74 /* (APHY_CALIB is for ADI usage only) */ 75 76 #define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ 77 78 #define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ 79 80 /* (PHY_TEST is for ADI usage only) */ 81 82 #define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ 83 84 #define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ 85 #define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ 86 87 /* USB Endpoint 0 Control Registers */ 88 89 #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ 90 #define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ 91 #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ 92 #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ 93 #define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ 94 #define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ 95 #define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ 96 #define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ 97 #define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ 98 #define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ 99 100 /* USB Endpoint 1 Control Registers */ 101 102 #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ 103 #define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ 104 #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ 105 #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ 106 #define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ 107 #define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ 108 #define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ 109 #define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ 110 #define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ 111 #define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ 112 113 /* USB Endpoint 2 Control Registers */ 114 115 #define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ 116 #define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ 117 #define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ 118 #define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ 119 #define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ 120 #define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ 121 #define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ 122 #define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ 123 #define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ 124 #define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ 125 126 /* USB Endpoint 3 Control Registers */ 127 128 #define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ 129 #define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ 130 #define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ 131 #define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ 132 #define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ 133 #define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ 134 #define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ 135 #define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ 136 #define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ 137 #define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ 138 139 /* USB Endpoint 4 Control Registers */ 140 141 #define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ 142 #define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ 143 #define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ 144 #define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ 145 #define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ 146 #define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ 147 #define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ 148 #define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ 149 #define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ 150 #define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ 151 152 /* USB Endpoint 5 Control Registers */ 153 154 #define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ 155 #define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ 156 #define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ 157 #define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ 158 #define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ 159 #define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ 160 #define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ 161 #define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ 162 #define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ 163 #define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ 164 165 /* USB Endpoint 6 Control Registers */ 166 167 #define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ 168 #define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ 169 #define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ 170 #define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ 171 #define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ 172 #define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ 173 #define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ 174 #define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ 175 #define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ 176 #define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ 177 178 /* USB Endpoint 7 Control Registers */ 179 180 #define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ 181 #define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ 182 #define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ 183 #define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ 184 #define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ 185 #define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ 186 #define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ 187 #define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ 188 #define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ 189 #define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ 190 191 #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ 192 193 /* USB Channel 0 Config Registers */ 194 195 #define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ 196 #define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ 197 #define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ 198 #define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ 199 #define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ 200 201 /* USB Channel 1 Config Registers */ 202 203 #define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ 204 #define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ 205 #define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ 206 #define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ 207 #define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ 208 209 /* USB Channel 2 Config Registers */ 210 211 #define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ 212 #define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ 213 #define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ 214 #define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ 215 #define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ 216 217 /* USB Channel 3 Config Registers */ 218 219 #define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ 220 #define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ 221 #define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ 222 #define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ 223 #define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ 224 225 /* USB Channel 4 Config Registers */ 226 227 #define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ 228 #define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ 229 #define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ 230 #define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ 231 #define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ 232 233 /* USB Channel 5 Config Registers */ 234 235 #define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ 236 #define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ 237 #define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ 238 #define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ 239 #define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ 240 241 /* USB Channel 6 Config Registers */ 242 243 #define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ 244 #define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ 245 #define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ 246 #define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ 247 #define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ 248 249 /* USB Channel 7 Config Registers */ 250 251 #define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ 252 #define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ 253 #define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ 254 #define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ 255 #define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ 256 257 /* Bit masks for USB_FADDR */ 258 259 #define FUNCTION_ADDRESS 0x7f /* Function address */ 260 261 /* Bit masks for USB_POWER */ 262 263 #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ 264 #define nENABLE_SUSPENDM 0x0 265 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ 266 #define nSUSPEND_MODE 0x0 267 #define RESUME_MODE 0x4 /* DMA Mode */ 268 #define nRESUME_MODE 0x0 269 #define RESET 0x8 /* Reset indicator */ 270 #define nRESET 0x0 271 #define HS_MODE 0x10 /* High Speed mode indicator */ 272 #define nHS_MODE 0x0 273 #define HS_ENABLE 0x20 /* high Speed Enable */ 274 #define nHS_ENABLE 0x0 275 #define SOFT_CONN 0x40 /* Soft connect */ 276 #define nSOFT_CONN 0x0 277 #define ISO_UPDATE 0x80 /* Isochronous update */ 278 #define nISO_UPDATE 0x0 279 280 /* Bit masks for USB_INTRTX */ 281 282 #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ 283 #define nEP0_TX 0x0 284 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ 285 #define nEP1_TX 0x0 286 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ 287 #define nEP2_TX 0x0 288 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ 289 #define nEP3_TX 0x0 290 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ 291 #define nEP4_TX 0x0 292 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ 293 #define nEP5_TX 0x0 294 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ 295 #define nEP6_TX 0x0 296 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ 297 #define nEP7_TX 0x0 298 299 /* Bit masks for USB_INTRRX */ 300 301 #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ 302 #define nEP1_RX 0x0 303 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ 304 #define nEP2_RX 0x0 305 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ 306 #define nEP3_RX 0x0 307 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ 308 #define nEP4_RX 0x0 309 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ 310 #define nEP5_RX 0x0 311 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ 312 #define nEP6_RX 0x0 313 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ 314 #define nEP7_RX 0x0 315 316 /* Bit masks for USB_INTRTXE */ 317 318 #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ 319 #define nEP0_TX_E 0x0 320 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ 321 #define nEP1_TX_E 0x0 322 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ 323 #define nEP2_TX_E 0x0 324 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ 325 #define nEP3_TX_E 0x0 326 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ 327 #define nEP4_TX_E 0x0 328 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ 329 #define nEP5_TX_E 0x0 330 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ 331 #define nEP6_TX_E 0x0 332 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ 333 #define nEP7_TX_E 0x0 334 335 /* Bit masks for USB_INTRRXE */ 336 337 #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ 338 #define nEP1_RX_E 0x0 339 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ 340 #define nEP2_RX_E 0x0 341 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ 342 #define nEP3_RX_E 0x0 343 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ 344 #define nEP4_RX_E 0x0 345 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ 346 #define nEP5_RX_E 0x0 347 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ 348 #define nEP6_RX_E 0x0 349 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ 350 #define nEP7_RX_E 0x0 351 352 /* Bit masks for USB_INTRUSB */ 353 354 #define SUSPEND_B 0x1 /* Suspend indicator */ 355 #define nSUSPEND_B 0x0 356 #define RESUME_B 0x2 /* Resume indicator */ 357 #define nRESUME_B 0x0 358 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ 359 #define nRESET_OR_BABLE_B 0x0 360 #define SOF_B 0x8 /* Start of frame */ 361 #define nSOF_B 0x0 362 #define CONN_B 0x10 /* Connection indicator */ 363 #define nCONN_B 0x0 364 #define DISCON_B 0x20 /* Disconnect indicator */ 365 #define nDISCON_B 0x0 366 #define SESSION_REQ_B 0x40 /* Session Request */ 367 #define nSESSION_REQ_B 0x0 368 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ 369 #define nVBUS_ERROR_B 0x0 370 371 /* Bit masks for USB_INTRUSBE */ 372 373 #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ 374 #define nSUSPEND_BE 0x0 375 #define RESUME_BE 0x2 /* Resume indicator int enable */ 376 #define nRESUME_BE 0x0 377 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ 378 #define nRESET_OR_BABLE_BE 0x0 379 #define SOF_BE 0x8 /* Start of frame int enable */ 380 #define nSOF_BE 0x0 381 #define CONN_BE 0x10 /* Connection indicator int enable */ 382 #define nCONN_BE 0x0 383 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ 384 #define nDISCON_BE 0x0 385 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ 386 #define nSESSION_REQ_BE 0x0 387 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ 388 #define nVBUS_ERROR_BE 0x0 389 390 /* Bit masks for USB_FRAME */ 391 392 #define FRAME_NUMBER 0x7ff /* Frame number */ 393 394 /* Bit masks for USB_INDEX */ 395 396 #define SELECTED_ENDPOINT 0xf /* selected endpoint */ 397 398 /* Bit masks for USB_GLOBAL_CTL */ 399 400 #define GLOBAL_ENA 0x1 /* enables USB module */ 401 #define nGLOBAL_ENA 0x0 402 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ 403 #define nEP1_TX_ENA 0x0 404 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ 405 #define nEP2_TX_ENA 0x0 406 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ 407 #define nEP3_TX_ENA 0x0 408 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ 409 #define nEP4_TX_ENA 0x0 410 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ 411 #define nEP5_TX_ENA 0x0 412 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ 413 #define nEP6_TX_ENA 0x0 414 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ 415 #define nEP7_TX_ENA 0x0 416 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ 417 #define nEP1_RX_ENA 0x0 418 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ 419 #define nEP2_RX_ENA 0x0 420 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ 421 #define nEP3_RX_ENA 0x0 422 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ 423 #define nEP4_RX_ENA 0x0 424 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ 425 #define nEP5_RX_ENA 0x0 426 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ 427 #define nEP6_RX_ENA 0x0 428 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ 429 #define nEP7_RX_ENA 0x0 430 431 /* Bit masks for USB_OTG_DEV_CTL */ 432 433 #define SESSION 0x1 /* session indicator */ 434 #define nSESSION 0x0 435 #define HOST_REQ 0x2 /* Host negotiation request */ 436 #define nHOST_REQ 0x0 437 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ 438 #define nHOST_MODE 0x0 439 #define VBUS0 0x8 /* Vbus level indicator[0] */ 440 #define nVBUS0 0x0 441 #define VBUS1 0x10 /* Vbus level indicator[1] */ 442 #define nVBUS1 0x0 443 #define LSDEV 0x20 /* Low-speed indicator */ 444 #define nLSDEV 0x0 445 #define FSDEV 0x40 /* Full or High-speed indicator */ 446 #define nFSDEV 0x0 447 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ 448 #define nB_DEVICE 0x0 449 450 /* Bit masks for USB_OTG_VBUS_IRQ */ 451 452 #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ 453 #define nDRIVE_VBUS_ON 0x0 454 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ 455 #define nDRIVE_VBUS_OFF 0x0 456 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ 457 #define nCHRG_VBUS_START 0x0 458 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ 459 #define nCHRG_VBUS_END 0x0 460 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ 461 #define nDISCHRG_VBUS_START 0x0 462 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ 463 #define nDISCHRG_VBUS_END 0x0 464 465 /* Bit masks for USB_OTG_VBUS_MASK */ 466 467 #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ 468 #define nDRIVE_VBUS_ON_ENA 0x0 469 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ 470 #define nDRIVE_VBUS_OFF_ENA 0x0 471 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ 472 #define nCHRG_VBUS_START_ENA 0x0 473 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ 474 #define nCHRG_VBUS_END_ENA 0x0 475 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ 476 #define nDISCHRG_VBUS_START_ENA 0x0 477 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ 478 #define nDISCHRG_VBUS_END_ENA 0x0 479 480 /* Bit masks for USB_CSR0 */ 481 482 #define RXPKTRDY 0x1 /* data packet receive indicator */ 483 #define nRXPKTRDY 0x0 484 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ 485 #define nTXPKTRDY 0x0 486 #define STALL_SENT 0x4 /* STALL handshake sent */ 487 #define nSTALL_SENT 0x0 488 #define DATAEND 0x8 /* Data end indicator */ 489 #define nDATAEND 0x0 490 #define SETUPEND 0x10 /* Setup end */ 491 #define nSETUPEND 0x0 492 #define SENDSTALL 0x20 /* Send STALL handshake */ 493 #define nSENDSTALL 0x0 494 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ 495 #define nSERVICED_RXPKTRDY 0x0 496 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ 497 #define nSERVICED_SETUPEND 0x0 498 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ 499 #define nFLUSHFIFO 0x0 500 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ 501 #define nSTALL_RECEIVED_H 0x0 502 #define SETUPPKT_H 0x8 /* send Setup token host mode */ 503 #define nSETUPPKT_H 0x0 504 #define ERROR_H 0x10 /* timeout error indicator host mode */ 505 #define nERROR_H 0x0 506 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ 507 #define nREQPKT_H 0x0 508 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ 509 #define nSTATUSPKT_H 0x0 510 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ 511 #define nNAK_TIMEOUT_H 0x0 512 513 /* Bit masks for USB_COUNT0 */ 514 515 #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ 516 517 /* Bit masks for USB_NAKLIMIT0 */ 518 519 #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ 520 521 /* Bit masks for USB_TX_MAX_PACKET */ 522 523 #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ 524 525 /* Bit masks for USB_RX_MAX_PACKET */ 526 527 #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ 528 529 /* Bit masks for USB_TXCSR */ 530 531 #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ 532 #define nTXPKTRDY_T 0x0 533 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ 534 #define nFIFO_NOT_EMPTY_T 0x0 535 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ 536 #define nUNDERRUN_T 0x0 537 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ 538 #define nFLUSHFIFO_T 0x0 539 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ 540 #define nSTALL_SEND_T 0x0 541 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ 542 #define nSTALL_SENT_T 0x0 543 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ 544 #define nCLEAR_DATATOGGLE_T 0x0 545 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ 546 #define nINCOMPTX_T 0x0 547 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ 548 #define nDMAREQMODE_T 0x0 549 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ 550 #define nFORCE_DATATOGGLE_T 0x0 551 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ 552 #define nDMAREQ_ENA_T 0x0 553 #define ISO_T 0x4000 /* enable Isochronous transfers */ 554 #define nISO_T 0x0 555 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ 556 #define nAUTOSET_T 0x0 557 #define ERROR_TH 0x4 /* error condition host mode */ 558 #define nERROR_TH 0x0 559 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ 560 #define nSTALL_RECEIVED_TH 0x0 561 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ 562 #define nNAK_TIMEOUT_TH 0x0 563 564 /* Bit masks for USB_TXCOUNT */ 565 566 #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ 567 568 /* Bit masks for USB_RXCSR */ 569 570 #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ 571 #define nRXPKTRDY_R 0x0 572 #define FIFO_FULL_R 0x2 /* FIFO not empty */ 573 #define nFIFO_FULL_R 0x0 574 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ 575 #define nOVERRUN_R 0x0 576 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ 577 #define nDATAERROR_R 0x0 578 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ 579 #define nFLUSHFIFO_R 0x0 580 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ 581 #define nSTALL_SEND_R 0x0 582 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ 583 #define nSTALL_SENT_R 0x0 584 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ 585 #define nCLEAR_DATATOGGLE_R 0x0 586 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ 587 #define nINCOMPRX_R 0x0 588 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ 589 #define nDMAREQMODE_R 0x0 590 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ 591 #define nDISNYET_R 0x0 592 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ 593 #define nDMAREQ_ENA_R 0x0 594 #define ISO_R 0x4000 /* enable Isochronous transfers */ 595 #define nISO_R 0x0 596 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ 597 #define nAUTOCLEAR_R 0x0 598 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ 599 #define nERROR_RH 0x0 600 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ 601 #define nREQPKT_RH 0x0 602 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ 603 #define nSTALL_RECEIVED_RH 0x0 604 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ 605 #define nINCOMPRX_RH 0x0 606 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ 607 #define nDMAREQMODE_RH 0x0 608 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ 609 #define nAUTOREQ_RH 0x0 610 611 /* Bit masks for USB_RXCOUNT */ 612 613 #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ 614 615 /* Bit masks for USB_TXTYPE */ 616 617 #define TARGET_EP_NO_T 0xf /* EP number */ 618 #define PROTOCOL_T 0xc /* transfer type */ 619 620 /* Bit masks for USB_TXINTERVAL */ 621 622 #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ 623 624 /* Bit masks for USB_RXTYPE */ 625 626 #define TARGET_EP_NO_R 0xf /* EP number */ 627 #define PROTOCOL_R 0xc /* transfer type */ 628 629 /* Bit masks for USB_RXINTERVAL */ 630 631 #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ 632 633 /* Bit masks for USB_DMA_INTERRUPT */ 634 635 #define DMA0_INT 0x1 /* DMA0 pending interrupt */ 636 #define nDMA0_INT 0x0 637 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ 638 #define nDMA1_INT 0x0 639 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ 640 #define nDMA2_INT 0x0 641 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ 642 #define nDMA3_INT 0x0 643 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ 644 #define nDMA4_INT 0x0 645 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ 646 #define nDMA5_INT 0x0 647 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ 648 #define nDMA6_INT 0x0 649 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ 650 #define nDMA7_INT 0x0 651 652 /* Bit masks for USB_DMAxCONTROL */ 653 654 #define DMA_ENA 0x1 /* DMA enable */ 655 #define nDMA_ENA 0x0 656 #define DIRECTION 0x2 /* direction of DMA transfer */ 657 #define nDIRECTION 0x0 658 #define MODE 0x4 /* DMA Bus error */ 659 #define nMODE 0x0 660 #define INT_ENA 0x8 /* Interrupt enable */ 661 #define nINT_ENA 0x0 662 #define EPNUM 0xf0 /* EP number */ 663 #define BUSERROR 0x100 /* DMA Bus error */ 664 #define nBUSERROR 0x0 665 666 /* Bit masks for USB_DMAxADDRHIGH */ 667 668 #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ 669 670 /* Bit masks for USB_DMAxADDRLOW */ 671 672 #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ 673 674 /* Bit masks for USB_DMAxCOUNTHIGH */ 675 676 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ 677 678 /* Bit masks for USB_DMAxCOUNTLOW */ 679 680 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ 681 682 #endif /* _DEF_BF525_H */ 683