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Searched refs:mult_div1_reg (Results 1 – 8 of 8) sorted by relevance

/linux-3.4.99/arch/arm/mach-omap2/
Dclkt2xxx_dpllcore.c135 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); in omap2_reprogram_dpllcore()
Ddpll3xxx.c315 v = __raw_readl(dd->mult_div1_reg); in omap3_noncore_dpll_program()
332 __raw_writel(v, dd->mult_div1_reg); in omap3_noncore_dpll_program()
Dclkt_dpll.c267 v = __raw_readl(dd->mult_div1_reg); in omap2_get_dpll_rate()
Dclock44xx_data.c253 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
429 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
667 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
735 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
808 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
952 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
Dclock3xxx_data.c277 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
348 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
409 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
566 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
588 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
920 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
Dclock2420_data.c109 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Dclock2430_data.c108 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
/linux-3.4.99/arch/arm/plat-omap/include/plat/
Dclock.h145 void __iomem *mult_div1_reg; member