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Searched refs:mstp_clks (Results 1 – 15 of 15) sorted by relevance

/linux-3.4.99/arch/sh/kernel/cpu/sh4a/
Dclock-sh7723.c153 static struct clk mstp_clks[] = { variable
228 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
229 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
230 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
231 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
232 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
233 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
234 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
235 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
236 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
[all …]
Dclock-sh7786.c93 static struct clk mstp_clks[MSTP_NR] = { variable
142 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]),
143 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]),
144 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
145 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
146 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
147 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
149 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
150 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
151 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
[all …]
Dclock-sh7724.c214 static struct clk mstp_clks[HWBLK_NR] = { variable
294 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
295 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
296 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
297 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
298 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
299 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
300 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
301 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
302 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
[all …]
Dclock-sh7343.c150 static struct clk mstp_clks[MSTP_NR] = { variable
218 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
219 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
220 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
221 CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
222 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
223 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
224 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
225 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
226 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
[all …]
Dclock-sh7366.c152 static struct clk mstp_clks[MSTP_NR] = { variable
216 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
217 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
218 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
219 CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
220 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
221 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
222 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
223 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
224 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
[all …]
Dclock-sh7785.c92 static struct clk mstp_clks[MSTP_NR] = { variable
135 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]),
136 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]),
137 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
138 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
139 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
140 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
142 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
143 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
144 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
[all …]
Dclock-sh7757.c86 static struct clk mstp_clks[MSTP_NR] = { variable
116 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP004]),
117 CLKDEV_CON_ID("riic0", &mstp_clks[MSTP000]),
118 CLKDEV_CON_ID("riic1", &mstp_clks[MSTP000]),
119 CLKDEV_CON_ID("riic2", &mstp_clks[MSTP000]),
120 CLKDEV_CON_ID("riic3", &mstp_clks[MSTP000]),
121 CLKDEV_CON_ID("riic4", &mstp_clks[MSTP000]),
122 CLKDEV_CON_ID("riic5", &mstp_clks[MSTP000]),
123 CLKDEV_CON_ID("riic6", &mstp_clks[MSTP000]),
124 CLKDEV_CON_ID("riic7", &mstp_clks[MSTP000]),
[all …]
Dclock-shx3.c84 static struct clk mstp_clks[MSTP_NR] = { variable
117 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
118 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
119 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
120 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
122 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
123 CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
124 CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
125 CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
127 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP008]),
[all …]
Dclock-sh7722.c153 static struct clk mstp_clks[HWBLK_NR] = { variable
203 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
204 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
206 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU]),
207 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU]),
208 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]),
210 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
211 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
212 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
214 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
[all …]
/linux-3.4.99/arch/arm/mach-shmobile/
Dclock-sh7372.c522 static struct clk mstp_clks[MSTP_NR] = { variable
620 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
621 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
622 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
623 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
624 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
625 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
626 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
627 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
628 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
[all …]
Dclock-sh7367.c231 static struct clk mstp_clks[MSTP_NR] = { variable
302 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
303 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
304 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
305 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
306 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
307 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
308 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
309 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
310 CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
[all …]
Dclock-sh7377.c242 static struct clk mstp_clks[] = { variable
315 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
316 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
317 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
318 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
319 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
320 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
321 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
322 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
323 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
[all …]
Dclock-sh73a0.c489 static struct clk mstp_clks[MSTP_NR] = { variable
544 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
545 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
546 CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
547 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
548 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
549 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
550 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
551 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
552 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
[all …]
Dclock-r8a7740.c265 static struct clk mstp_clks[MSTP_NR] = { variable
319 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
320 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
321 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
322 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
323 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
325 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
326 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
327 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
328 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
[all …]
Dclock-r8a7779.c93 static struct clk mstp_clks[MSTP_NR] = { variable
144 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
145 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
146 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
147 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
148 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
149 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
150 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
151 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
165 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); in r8a7779_clock_init()