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Searched refs:link_width_cntl (Results 1 – 4 of 4) sorted by relevance

/linux-3.4.99/drivers/gpu/drm/radeon/
Drv770.c1307 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
1324 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
1325 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
1326 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
1327 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
1328 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
1329 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
1330 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
1332 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
1334 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
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Dr300.c491 uint32_t link_width_cntl, mask; in rv370_set_pcie_lanes() local
526 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
528 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == in rv370_set_pcie_lanes()
532 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | in rv370_set_pcie_lanes()
536 link_width_cntl |= mask; in rv370_set_pcie_lanes()
537 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv370_set_pcie_lanes()
538 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | in rv370_set_pcie_lanes()
542 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
543 while (link_width_cntl == 0xffffffff) in rv370_set_pcie_lanes()
544 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
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Dr600.c3588 u32 link_width_cntl, mask, target_reg; in r600_set_pcie_lanes() local
3627 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_set_pcie_lanes()
3629 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == in r600_set_pcie_lanes()
3633 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) in r600_set_pcie_lanes()
3636 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | in r600_set_pcie_lanes()
3640 link_width_cntl |= mask; in r600_set_pcie_lanes()
3642 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in r600_set_pcie_lanes()
3648 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) in r600_set_pcie_lanes()
3649 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; in r600_set_pcie_lanes()
3651 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; in r600_set_pcie_lanes()
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Devergreen.c3502 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
3521 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
3522 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
3523 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
3542 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
3545 link_width_cntl |= LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
3547 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
3548 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()