1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-trans.h"
72 #include "iwl-trans-pcie-int.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-shared.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
78
79 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
80
81 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
82 (((1<<cfg(trans)->base_params->num_of_queues) - 1) &\
83 (~(1<<(trans_pcie)->cmd_queue)))
84
iwl_trans_rx_alloc(struct iwl_trans * trans)85 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
86 {
87 struct iwl_trans_pcie *trans_pcie =
88 IWL_TRANS_GET_PCIE_TRANS(trans);
89 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
90 struct device *dev = trans->dev;
91
92 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
93
94 spin_lock_init(&rxq->lock);
95
96 if (WARN_ON(rxq->bd || rxq->rb_stts))
97 return -EINVAL;
98
99 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
100 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
101 &rxq->bd_dma, GFP_KERNEL);
102 if (!rxq->bd)
103 goto err_bd;
104
105 /*Allocate the driver's pointer to receive buffer status */
106 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
107 &rxq->rb_stts_dma, GFP_KERNEL);
108 if (!rxq->rb_stts)
109 goto err_rb_stts;
110
111 return 0;
112
113 err_rb_stts:
114 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
115 rxq->bd, rxq->bd_dma);
116 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
117 rxq->bd = NULL;
118 err_bd:
119 return -ENOMEM;
120 }
121
iwl_trans_rxq_free_rx_bufs(struct iwl_trans * trans)122 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
123 {
124 struct iwl_trans_pcie *trans_pcie =
125 IWL_TRANS_GET_PCIE_TRANS(trans);
126 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
127 int i;
128
129 /* Fill the rx_used queue with _all_ of the Rx buffers */
130 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
131 /* In the reset function, these buffers may have been allocated
132 * to an SKB, so we need to unmap and free potential storage */
133 if (rxq->pool[i].page != NULL) {
134 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
135 PAGE_SIZE << hw_params(trans).rx_page_order,
136 DMA_FROM_DEVICE);
137 __free_pages(rxq->pool[i].page,
138 hw_params(trans).rx_page_order);
139 rxq->pool[i].page = NULL;
140 }
141 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
142 }
143 }
144
iwl_trans_rx_hw_init(struct iwl_trans * trans,struct iwl_rx_queue * rxq)145 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
146 struct iwl_rx_queue *rxq)
147 {
148 u32 rb_size;
149 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
150 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
151
152 if (iwlagn_mod_params.amsdu_size_8K)
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
154 else
155 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
156
157 /* Stop Rx DMA */
158 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
159
160 /* Reset driver's Rx queue write index */
161 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
162
163 /* Tell device where to find RBD circular buffer in DRAM */
164 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
165 (u32)(rxq->bd_dma >> 8));
166
167 /* Tell device where in DRAM to update its Rx status */
168 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
169 rxq->rb_stts_dma >> 4);
170
171 /* Enable Rx DMA
172 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
173 * the credit mechanism in 5000 HW RX FIFO
174 * Direct rx interrupts to hosts
175 * Rx buffer size 4 or 8k
176 * RB timeout 0x10
177 * 256 RBDs
178 */
179 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
180 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
181 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
182 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
183 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
184 rb_size|
185 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
186 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
187
188 /* Set interrupt coalescing timer to default (2048 usecs) */
189 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
190 }
191
iwl_rx_init(struct iwl_trans * trans)192 static int iwl_rx_init(struct iwl_trans *trans)
193 {
194 struct iwl_trans_pcie *trans_pcie =
195 IWL_TRANS_GET_PCIE_TRANS(trans);
196 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
197
198 int i, err;
199 unsigned long flags;
200
201 if (!rxq->bd) {
202 err = iwl_trans_rx_alloc(trans);
203 if (err)
204 return err;
205 }
206
207 spin_lock_irqsave(&rxq->lock, flags);
208 INIT_LIST_HEAD(&rxq->rx_free);
209 INIT_LIST_HEAD(&rxq->rx_used);
210
211 iwl_trans_rxq_free_rx_bufs(trans);
212
213 for (i = 0; i < RX_QUEUE_SIZE; i++)
214 rxq->queue[i] = NULL;
215
216 /* Set us so that we have processed and used all buffers, but have
217 * not restocked the Rx queue with fresh buffers */
218 rxq->read = rxq->write = 0;
219 rxq->write_actual = 0;
220 rxq->free_count = 0;
221 spin_unlock_irqrestore(&rxq->lock, flags);
222
223 iwlagn_rx_replenish(trans);
224
225 iwl_trans_rx_hw_init(trans, rxq);
226
227 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
228 rxq->need_update = 1;
229 iwl_rx_queue_update_write_ptr(trans, rxq);
230 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
231
232 return 0;
233 }
234
iwl_trans_pcie_rx_free(struct iwl_trans * trans)235 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
236 {
237 struct iwl_trans_pcie *trans_pcie =
238 IWL_TRANS_GET_PCIE_TRANS(trans);
239 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
240
241 unsigned long flags;
242
243 /*if rxq->bd is NULL, it means that nothing has been allocated,
244 * exit now */
245 if (!rxq->bd) {
246 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
247 return;
248 }
249
250 spin_lock_irqsave(&rxq->lock, flags);
251 iwl_trans_rxq_free_rx_bufs(trans);
252 spin_unlock_irqrestore(&rxq->lock, flags);
253
254 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
255 rxq->bd, rxq->bd_dma);
256 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
257 rxq->bd = NULL;
258
259 if (rxq->rb_stts)
260 dma_free_coherent(trans->dev,
261 sizeof(struct iwl_rb_status),
262 rxq->rb_stts, rxq->rb_stts_dma);
263 else
264 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
265 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
266 rxq->rb_stts = NULL;
267 }
268
iwl_trans_rx_stop(struct iwl_trans * trans)269 static int iwl_trans_rx_stop(struct iwl_trans *trans)
270 {
271
272 /* stop Rx DMA */
273 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
274 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
275 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
276 }
277
iwlagn_alloc_dma_ptr(struct iwl_trans * trans,struct iwl_dma_ptr * ptr,size_t size)278 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
279 struct iwl_dma_ptr *ptr, size_t size)
280 {
281 if (WARN_ON(ptr->addr))
282 return -EINVAL;
283
284 ptr->addr = dma_alloc_coherent(trans->dev, size,
285 &ptr->dma, GFP_KERNEL);
286 if (!ptr->addr)
287 return -ENOMEM;
288 ptr->size = size;
289 return 0;
290 }
291
iwlagn_free_dma_ptr(struct iwl_trans * trans,struct iwl_dma_ptr * ptr)292 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
293 struct iwl_dma_ptr *ptr)
294 {
295 if (unlikely(!ptr->addr))
296 return;
297
298 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
299 memset(ptr, 0, sizeof(*ptr));
300 }
301
iwl_trans_txq_alloc(struct iwl_trans * trans,struct iwl_tx_queue * txq,int slots_num,u32 txq_id)302 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
303 struct iwl_tx_queue *txq, int slots_num,
304 u32 txq_id)
305 {
306 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
307 int i;
308 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
309
310 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
311 return -EINVAL;
312
313 txq->q.n_window = slots_num;
314
315 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
316 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
317
318 if (!txq->meta || !txq->cmd)
319 goto error;
320
321 if (txq_id == trans_pcie->cmd_queue)
322 for (i = 0; i < slots_num; i++) {
323 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
324 GFP_KERNEL);
325 if (!txq->cmd[i])
326 goto error;
327 }
328
329 /* Alloc driver data array and TFD circular buffer */
330 /* Driver private data, only for Tx (not command) queues,
331 * not shared with device. */
332 if (txq_id != trans_pcie->cmd_queue) {
333 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
334 GFP_KERNEL);
335 if (!txq->skbs) {
336 IWL_ERR(trans, "kmalloc for auxiliary BD "
337 "structures failed\n");
338 goto error;
339 }
340 } else {
341 txq->skbs = NULL;
342 }
343
344 /* Circular buffer of transmit frame descriptors (TFDs),
345 * shared with device */
346 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
347 &txq->q.dma_addr, GFP_KERNEL);
348 if (!txq->tfds) {
349 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
350 goto error;
351 }
352 txq->q.id = txq_id;
353
354 return 0;
355 error:
356 kfree(txq->skbs);
357 txq->skbs = NULL;
358 /* since txq->cmd has been zeroed,
359 * all non allocated cmd[i] will be NULL */
360 if (txq->cmd && txq_id == trans_pcie->cmd_queue)
361 for (i = 0; i < slots_num; i++)
362 kfree(txq->cmd[i]);
363 kfree(txq->meta);
364 kfree(txq->cmd);
365 txq->meta = NULL;
366 txq->cmd = NULL;
367
368 return -ENOMEM;
369
370 }
371
iwl_trans_txq_init(struct iwl_trans * trans,struct iwl_tx_queue * txq,int slots_num,u32 txq_id)372 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
373 int slots_num, u32 txq_id)
374 {
375 int ret;
376
377 txq->need_update = 0;
378 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
379
380 /*
381 * For the default queues 0-3, set up the swq_id
382 * already -- all others need to get one later
383 * (if they need one at all).
384 */
385 if (txq_id < 4)
386 iwl_set_swq_id(txq, txq_id, txq_id);
387
388 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
389 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
390 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
391
392 /* Initialize queue's high/low-water marks, and head/tail indexes */
393 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
394 txq_id);
395 if (ret)
396 return ret;
397
398 spin_lock_init(&txq->lock);
399
400 /*
401 * Tell nic where to find circular buffer of Tx Frame Descriptors for
402 * given Tx queue, and enable the DMA channel used for that queue.
403 * Circular buffer (TFD queue in DRAM) physical base address */
404 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
405 txq->q.dma_addr >> 8);
406
407 return 0;
408 }
409
410 /**
411 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
412 */
iwl_tx_queue_unmap(struct iwl_trans * trans,int txq_id)413 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
414 {
415 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
416 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
417 struct iwl_queue *q = &txq->q;
418 enum dma_data_direction dma_dir;
419
420 if (!q->n_bd)
421 return;
422
423 /* In the command queue, all the TBs are mapped as BIDI
424 * so unmap them as such.
425 */
426 if (txq_id == trans_pcie->cmd_queue)
427 dma_dir = DMA_BIDIRECTIONAL;
428 else
429 dma_dir = DMA_TO_DEVICE;
430
431 spin_lock_bh(&txq->lock);
432 while (q->write_ptr != q->read_ptr) {
433 iwlagn_txq_free_tfd(trans, txq, dma_dir);
434 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
435 }
436 spin_unlock_bh(&txq->lock);
437 }
438
439 /**
440 * iwl_tx_queue_free - Deallocate DMA queue.
441 * @txq: Transmit queue to deallocate.
442 *
443 * Empty queue by removing and destroying all BD's.
444 * Free all buffers.
445 * 0-fill, but do not free "txq" descriptor structure.
446 */
iwl_tx_queue_free(struct iwl_trans * trans,int txq_id)447 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
448 {
449 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
450 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
451 struct device *dev = trans->dev;
452 int i;
453 if (WARN_ON(!txq))
454 return;
455
456 iwl_tx_queue_unmap(trans, txq_id);
457
458 /* De-alloc array of command/tx buffers */
459
460 if (txq_id == trans_pcie->cmd_queue)
461 for (i = 0; i < txq->q.n_window; i++)
462 kfree(txq->cmd[i]);
463
464 /* De-alloc circular buffer of TFDs */
465 if (txq->q.n_bd) {
466 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
467 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
468 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
469 }
470
471 /* De-alloc array of per-TFD driver data */
472 kfree(txq->skbs);
473 txq->skbs = NULL;
474
475 /* deallocate arrays */
476 kfree(txq->cmd);
477 kfree(txq->meta);
478 txq->cmd = NULL;
479 txq->meta = NULL;
480
481 /* 0-fill queue descriptor structure */
482 memset(txq, 0, sizeof(*txq));
483 }
484
485 /**
486 * iwl_trans_tx_free - Free TXQ Context
487 *
488 * Destroy all TX DMA queues and structures
489 */
iwl_trans_pcie_tx_free(struct iwl_trans * trans)490 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
491 {
492 int txq_id;
493 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
494
495 /* Tx queues */
496 if (trans_pcie->txq) {
497 for (txq_id = 0;
498 txq_id < cfg(trans)->base_params->num_of_queues; txq_id++)
499 iwl_tx_queue_free(trans, txq_id);
500 }
501
502 kfree(trans_pcie->txq);
503 trans_pcie->txq = NULL;
504
505 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
506
507 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
508 }
509
510 /**
511 * iwl_trans_tx_alloc - allocate TX context
512 * Allocate all Tx DMA structures and initialize them
513 *
514 * @param priv
515 * @return error code
516 */
iwl_trans_tx_alloc(struct iwl_trans * trans)517 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
518 {
519 int ret;
520 int txq_id, slots_num;
521 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
522
523 u16 scd_bc_tbls_size = cfg(trans)->base_params->num_of_queues *
524 sizeof(struct iwlagn_scd_bc_tbl);
525
526 /*It is not allowed to alloc twice, so warn when this happens.
527 * We cannot rely on the previous allocation, so free and fail */
528 if (WARN_ON(trans_pcie->txq)) {
529 ret = -EINVAL;
530 goto error;
531 }
532
533 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
534 scd_bc_tbls_size);
535 if (ret) {
536 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
537 goto error;
538 }
539
540 /* Alloc keep-warm buffer */
541 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
542 if (ret) {
543 IWL_ERR(trans, "Keep Warm allocation failed\n");
544 goto error;
545 }
546
547 trans_pcie->txq = kcalloc(cfg(trans)->base_params->num_of_queues,
548 sizeof(struct iwl_tx_queue), GFP_KERNEL);
549 if (!trans_pcie->txq) {
550 IWL_ERR(trans, "Not enough memory for txq\n");
551 ret = ENOMEM;
552 goto error;
553 }
554
555 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
556 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
557 txq_id++) {
558 slots_num = (txq_id == trans_pcie->cmd_queue) ?
559 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
560 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
561 slots_num, txq_id);
562 if (ret) {
563 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
564 goto error;
565 }
566 }
567
568 return 0;
569
570 error:
571 iwl_trans_pcie_tx_free(trans);
572
573 return ret;
574 }
iwl_tx_init(struct iwl_trans * trans)575 static int iwl_tx_init(struct iwl_trans *trans)
576 {
577 int ret;
578 int txq_id, slots_num;
579 unsigned long flags;
580 bool alloc = false;
581 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
582
583 if (!trans_pcie->txq) {
584 ret = iwl_trans_tx_alloc(trans);
585 if (ret)
586 goto error;
587 alloc = true;
588 }
589
590 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
591
592 /* Turn off all Tx DMA fifos */
593 iwl_write_prph(trans, SCD_TXFACT, 0);
594
595 /* Tell NIC where to find the "keep warm" buffer */
596 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
597 trans_pcie->kw.dma >> 4);
598
599 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
600
601 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
602 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
603 txq_id++) {
604 slots_num = (txq_id == trans_pcie->cmd_queue) ?
605 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
606 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
607 slots_num, txq_id);
608 if (ret) {
609 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
610 goto error;
611 }
612 }
613
614 return 0;
615 error:
616 /*Upon error, free only if we allocated something */
617 if (alloc)
618 iwl_trans_pcie_tx_free(trans);
619 return ret;
620 }
621
iwl_set_pwr_vmain(struct iwl_trans * trans)622 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
623 {
624 /*
625 * (for documentation purposes)
626 * to set power to V_AUX, do:
627
628 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
629 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
630 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
631 ~APMG_PS_CTRL_MSK_PWR_SRC);
632 */
633
634 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
635 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
636 ~APMG_PS_CTRL_MSK_PWR_SRC);
637 }
638
639 /* PCI registers */
640 #define PCI_CFG_RETRY_TIMEOUT 0x041
641 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
642 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
643
iwl_pciexp_link_ctrl(struct iwl_trans * trans)644 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
645 {
646 int pos;
647 u16 pci_lnk_ctl;
648 struct iwl_trans_pcie *trans_pcie =
649 IWL_TRANS_GET_PCIE_TRANS(trans);
650
651 struct pci_dev *pci_dev = trans_pcie->pci_dev;
652
653 pos = pci_pcie_cap(pci_dev);
654 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
655 return pci_lnk_ctl;
656 }
657
iwl_apm_config(struct iwl_trans * trans)658 static void iwl_apm_config(struct iwl_trans *trans)
659 {
660 /*
661 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
662 * Check if BIOS (or OS) enabled L1-ASPM on this device.
663 * If so (likely), disable L0S, so device moves directly L0->L1;
664 * costs negligible amount of power savings.
665 * If not (unlikely), enable L0S, so there is at least some
666 * power savings, even without L1.
667 */
668 u16 lctl = iwl_pciexp_link_ctrl(trans);
669
670 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
671 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
672 /* L1-ASPM enabled; disable(!) L0S */
673 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
674 dev_printk(KERN_INFO, trans->dev,
675 "L1 Enabled; Disabling L0S\n");
676 } else {
677 /* L1-ASPM disabled; enable(!) L0S */
678 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
679 dev_printk(KERN_INFO, trans->dev,
680 "L1 Disabled; Enabling L0S\n");
681 }
682 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
683 }
684
685 /*
686 * Start up NIC's basic functionality after it has been reset
687 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
688 * NOTE: This does not load uCode nor start the embedded processor
689 */
iwl_apm_init(struct iwl_trans * trans)690 static int iwl_apm_init(struct iwl_trans *trans)
691 {
692 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
693 int ret = 0;
694 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
695
696 /*
697 * Use "set_bit" below rather than "write", to preserve any hardware
698 * bits already set by default after reset.
699 */
700
701 /* Disable L0S exit timer (platform NMI Work/Around) */
702 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
703 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
704
705 /*
706 * Disable L0s without affecting L1;
707 * don't wait for ICH L0s (ICH bug W/A)
708 */
709 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
710 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
711
712 /* Set FH wait threshold to maximum (HW error during stress W/A) */
713 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
714
715 /*
716 * Enable HAP INTA (interrupt from management bus) to
717 * wake device's PCI Express link L1a -> L0s
718 */
719 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
720 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
721
722 iwl_apm_config(trans);
723
724 /* Configure analog phase-lock-loop before activating to D0A */
725 if (cfg(trans)->base_params->pll_cfg_val)
726 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
727 cfg(trans)->base_params->pll_cfg_val);
728
729 /*
730 * Set "initialization complete" bit to move adapter from
731 * D0U* --> D0A* (powered-up active) state.
732 */
733 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
734
735 /*
736 * Wait for clock stabilization; once stabilized, access to
737 * device-internal resources is supported, e.g. iwl_write_prph()
738 * and accesses to uCode SRAM.
739 */
740 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
741 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
742 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
743 if (ret < 0) {
744 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
745 goto out;
746 }
747
748 /*
749 * Enable DMA clock and wait for it to stabilize.
750 *
751 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
752 * do not disable clocks. This preserves any hardware bits already
753 * set by default in "CLK_CTRL_REG" after reset.
754 */
755 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
756 udelay(20);
757
758 /* Disable L1-Active */
759 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
760 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
761
762 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
763
764 out:
765 return ret;
766 }
767
iwl_apm_stop_master(struct iwl_trans * trans)768 static int iwl_apm_stop_master(struct iwl_trans *trans)
769 {
770 int ret = 0;
771
772 /* stop device's busmaster DMA activity */
773 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
774
775 ret = iwl_poll_bit(trans, CSR_RESET,
776 CSR_RESET_REG_FLAG_MASTER_DISABLED,
777 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
778 if (ret)
779 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
780
781 IWL_DEBUG_INFO(trans, "stop master\n");
782
783 return ret;
784 }
785
iwl_apm_stop(struct iwl_trans * trans)786 static void iwl_apm_stop(struct iwl_trans *trans)
787 {
788 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
789 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
790
791 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
792
793 /* Stop device's DMA activity */
794 iwl_apm_stop_master(trans);
795
796 /* Reset the entire device */
797 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
798
799 udelay(10);
800
801 /*
802 * Clear "initialization complete" bit to move adapter from
803 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
804 */
805 iwl_clear_bit(trans, CSR_GP_CNTRL,
806 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
807 }
808
iwl_nic_init(struct iwl_trans * trans)809 static int iwl_nic_init(struct iwl_trans *trans)
810 {
811 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
812 unsigned long flags;
813
814 /* nic_init */
815 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
816 iwl_apm_init(trans);
817
818 /* Set interrupt coalescing calibration timer to default (512 usecs) */
819 iwl_write8(trans, CSR_INT_COALESCING,
820 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
821
822 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
823
824 iwl_set_pwr_vmain(trans);
825
826 iwl_op_mode_nic_config(trans->op_mode);
827
828 #ifndef CONFIG_IWLWIFI_IDI
829 /* Allocate the RX queue, or reset if it is already allocated */
830 iwl_rx_init(trans);
831 #endif
832
833 /* Allocate or reset and init all Tx and Command queues */
834 if (iwl_tx_init(trans))
835 return -ENOMEM;
836
837 if (cfg(trans)->base_params->shadow_reg_enable) {
838 /* enable shadow regs in HW */
839 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
840 0x800FFFFF);
841 }
842
843 return 0;
844 }
845
846 #define HW_READY_TIMEOUT (50)
847
848 /* Note: returns poll_bit return value, which is >= 0 if success */
iwl_set_hw_ready(struct iwl_trans * trans)849 static int iwl_set_hw_ready(struct iwl_trans *trans)
850 {
851 int ret;
852
853 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
854 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
855
856 /* See if we got it */
857 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
858 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
859 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
860 HW_READY_TIMEOUT);
861
862 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
863 return ret;
864 }
865
866 /* Note: returns standard 0/-ERROR code */
iwl_prepare_card_hw(struct iwl_trans * trans)867 static int iwl_prepare_card_hw(struct iwl_trans *trans)
868 {
869 int ret;
870
871 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
872
873 ret = iwl_set_hw_ready(trans);
874 /* If the card is ready, exit 0 */
875 if (ret >= 0)
876 return 0;
877
878 /* If HW is not ready, prepare the conditions to check again */
879 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
880 CSR_HW_IF_CONFIG_REG_PREPARE);
881
882 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
883 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
884 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
885
886 if (ret < 0)
887 return ret;
888
889 /* HW should be ready by now, check again. */
890 ret = iwl_set_hw_ready(trans);
891 if (ret >= 0)
892 return 0;
893 return ret;
894 }
895
896 #define IWL_AC_UNSET -1
897
898 struct queue_to_fifo_ac {
899 s8 fifo, ac;
900 };
901
902 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
903 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
904 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
905 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
906 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
907 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
908 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
909 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
910 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
911 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
912 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
913 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
914 };
915
916 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
917 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
918 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
919 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
920 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
921 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
922 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
923 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
924 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
925 { IWL_TX_FIFO_BE_IPAN, 2, },
926 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
927 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
928 };
929
930 static const u8 iwlagn_bss_ac_to_fifo[] = {
931 IWL_TX_FIFO_VO,
932 IWL_TX_FIFO_VI,
933 IWL_TX_FIFO_BE,
934 IWL_TX_FIFO_BK,
935 };
936 static const u8 iwlagn_bss_ac_to_queue[] = {
937 0, 1, 2, 3,
938 };
939 static const u8 iwlagn_pan_ac_to_fifo[] = {
940 IWL_TX_FIFO_VO_IPAN,
941 IWL_TX_FIFO_VI_IPAN,
942 IWL_TX_FIFO_BE_IPAN,
943 IWL_TX_FIFO_BK_IPAN,
944 };
945 static const u8 iwlagn_pan_ac_to_queue[] = {
946 7, 6, 5, 4,
947 };
948
949 /*
950 * ucode
951 */
iwl_load_section(struct iwl_trans * trans,u8 section_num,const struct fw_desc * section)952 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
953 const struct fw_desc *section)
954 {
955 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
956 dma_addr_t phy_addr = section->p_addr;
957 u32 byte_cnt = section->len;
958 u32 dst_addr = section->offset;
959 int ret;
960
961 trans_pcie->ucode_write_complete = false;
962
963 iwl_write_direct32(trans,
964 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
965 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
966
967 iwl_write_direct32(trans,
968 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
969
970 iwl_write_direct32(trans,
971 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
972 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
973
974 iwl_write_direct32(trans,
975 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
976 (iwl_get_dma_hi_addr(phy_addr)
977 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
978
979 iwl_write_direct32(trans,
980 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
981 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
982 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
983 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
984
985 iwl_write_direct32(trans,
986 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
987 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
988 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
989 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
990
991 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
992 section_num);
993 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
994 trans_pcie->ucode_write_complete, 5 * HZ);
995 if (!ret) {
996 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
997 section_num);
998 return -ETIMEDOUT;
999 }
1000
1001 return 0;
1002 }
1003
iwl_load_given_ucode(struct iwl_trans * trans,const struct fw_img * image)1004 static int iwl_load_given_ucode(struct iwl_trans *trans,
1005 const struct fw_img *image)
1006 {
1007 int ret = 0;
1008 int i;
1009
1010 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
1011 if (!image->sec[i].p_addr)
1012 break;
1013
1014 ret = iwl_load_section(trans, i, &image->sec[i]);
1015 if (ret)
1016 return ret;
1017 }
1018
1019 /* Remove all resets to allow NIC to operate */
1020 iwl_write32(trans, CSR_RESET, 0);
1021
1022 return 0;
1023 }
1024
iwl_trans_pcie_start_fw(struct iwl_trans * trans,const struct fw_img * fw)1025 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1026 const struct fw_img *fw)
1027 {
1028 int ret;
1029 struct iwl_trans_pcie *trans_pcie =
1030 IWL_TRANS_GET_PCIE_TRANS(trans);
1031 bool hw_rfkill;
1032
1033 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1034 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1035
1036 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1037 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1038
1039 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1040 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1041
1042 /* This may fail if AMT took ownership of the device */
1043 if (iwl_prepare_card_hw(trans)) {
1044 IWL_WARN(trans, "Exit HW not ready\n");
1045 return -EIO;
1046 }
1047
1048 /* If platform's RF_KILL switch is NOT set to KILL */
1049 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1050 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1051 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1052
1053 if (hw_rfkill) {
1054 iwl_enable_rfkill_int(trans);
1055 return -ERFKILL;
1056 }
1057
1058 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1059
1060 ret = iwl_nic_init(trans);
1061 if (ret) {
1062 IWL_ERR(trans, "Unable to init nic\n");
1063 return ret;
1064 }
1065
1066 /* make sure rfkill handshake bits are cleared */
1067 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1068 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1069 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1070
1071 /* clear (again), then enable host interrupts */
1072 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1073 iwl_enable_interrupts(trans);
1074
1075 /* really make sure rfkill handshake bits are cleared */
1076 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1077 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1078
1079 /* Load the given image to the HW */
1080 return iwl_load_given_ucode(trans, fw);
1081 }
1082
1083 /*
1084 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1085 * must be called under the irq lock and with MAC access
1086 */
iwl_trans_txq_set_sched(struct iwl_trans * trans,u32 mask)1087 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1088 {
1089 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1090 IWL_TRANS_GET_PCIE_TRANS(trans);
1091
1092 lockdep_assert_held(&trans_pcie->irq_lock);
1093
1094 iwl_write_prph(trans, SCD_TXFACT, mask);
1095 }
1096
iwl_tx_start(struct iwl_trans * trans)1097 static void iwl_tx_start(struct iwl_trans *trans)
1098 {
1099 const struct queue_to_fifo_ac *queue_to_fifo;
1100 struct iwl_trans_pcie *trans_pcie =
1101 IWL_TRANS_GET_PCIE_TRANS(trans);
1102 u32 a;
1103 unsigned long flags;
1104 int i, chan;
1105 u32 reg_val;
1106
1107 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1108
1109 trans_pcie->scd_base_addr =
1110 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1111 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1112 /* reset conext data memory */
1113 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1114 a += 4)
1115 iwl_write_targ_mem(trans, a, 0);
1116 /* reset tx status memory */
1117 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1118 a += 4)
1119 iwl_write_targ_mem(trans, a, 0);
1120 for (; a < trans_pcie->scd_base_addr +
1121 SCD_TRANS_TBL_OFFSET_QUEUE(
1122 cfg(trans)->base_params->num_of_queues);
1123 a += 4)
1124 iwl_write_targ_mem(trans, a, 0);
1125
1126 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1127 trans_pcie->scd_bc_tbls.dma >> 10);
1128
1129 /* The chain extension of the SCD doesn't work well. This feature is
1130 * enabled by default by the HW, so we need to disable it manually.
1131 */
1132 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
1133
1134 /* Enable DMA channel */
1135 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1136 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1137 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1138 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1139
1140 /* Update FH chicken bits */
1141 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1142 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1143 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1144
1145 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1146 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
1147 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1148
1149 /* initiate the queues */
1150 for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) {
1151 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1152 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1153 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1154 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1155 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1156 SCD_CONTEXT_QUEUE_OFFSET(i) +
1157 sizeof(u32),
1158 ((SCD_WIN_SIZE <<
1159 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1160 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1161 ((SCD_FRAME_LIMIT <<
1162 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1163 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1164 }
1165
1166 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1167 IWL_MASK(0, cfg(trans)->base_params->num_of_queues));
1168
1169 /* Activate all Tx DMA/FIFO channels */
1170 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1171
1172 /* map queues to FIFOs */
1173 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1174 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1175 else
1176 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1177
1178 iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0);
1179
1180 /* make sure all queue are not stopped */
1181 memset(&trans_pcie->queue_stopped[0], 0,
1182 sizeof(trans_pcie->queue_stopped));
1183 for (i = 0; i < 4; i++)
1184 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1185
1186 /* reset to 0 to enable all the queue first */
1187 trans_pcie->txq_ctx_active_msk = 0;
1188
1189 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1190 IWLAGN_FIRST_AMPDU_QUEUE);
1191 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1192 IWLAGN_FIRST_AMPDU_QUEUE);
1193
1194 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1195 int fifo = queue_to_fifo[i].fifo;
1196 int ac = queue_to_fifo[i].ac;
1197
1198 iwl_txq_ctx_activate(trans_pcie, i);
1199
1200 if (fifo == IWL_TX_FIFO_UNUSED)
1201 continue;
1202
1203 if (ac != IWL_AC_UNSET)
1204 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1205 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1206 fifo, 0);
1207 }
1208
1209 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1210
1211 /* Enable L1-Active */
1212 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1213 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1214 }
1215
iwl_trans_pcie_fw_alive(struct iwl_trans * trans)1216 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1217 {
1218 iwl_reset_ict(trans);
1219 iwl_tx_start(trans);
1220 }
1221
1222 /**
1223 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1224 */
iwl_trans_tx_stop(struct iwl_trans * trans)1225 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1226 {
1227 int ch, txq_id, ret;
1228 unsigned long flags;
1229 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1230
1231 /* Turn off all Tx DMA fifos */
1232 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1233
1234 iwl_trans_txq_set_sched(trans, 0);
1235
1236 /* Stop each Tx DMA channel, and wait for it to be idle */
1237 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1238 iwl_write_direct32(trans,
1239 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1240 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1241 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1242 1000);
1243 if (ret < 0)
1244 IWL_ERR(trans, "Failing on timeout while stopping"
1245 " DMA channel %d [0x%08x]", ch,
1246 iwl_read_direct32(trans,
1247 FH_TSSR_TX_STATUS_REG));
1248 }
1249 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1250
1251 if (!trans_pcie->txq) {
1252 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1253 return 0;
1254 }
1255
1256 /* Unmap DMA from host system and free skb's */
1257 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
1258 txq_id++)
1259 iwl_tx_queue_unmap(trans, txq_id);
1260
1261 return 0;
1262 }
1263
iwl_trans_pcie_stop_device(struct iwl_trans * trans)1264 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1265 {
1266 unsigned long flags;
1267 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1268
1269 /* tell the device to stop sending interrupts */
1270 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1271 iwl_disable_interrupts(trans);
1272 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1273
1274 /* device going down, Stop using ICT table */
1275 iwl_disable_ict(trans);
1276
1277 /*
1278 * If a HW restart happens during firmware loading,
1279 * then the firmware loading might call this function
1280 * and later it might be called again due to the
1281 * restart. So don't process again if the device is
1282 * already dead.
1283 */
1284 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1285 iwl_trans_tx_stop(trans);
1286 #ifndef CONFIG_IWLWIFI_IDI
1287 iwl_trans_rx_stop(trans);
1288 #endif
1289 /* Power-down device's busmaster DMA clocks */
1290 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1291 APMG_CLK_VAL_DMA_CLK_RQT);
1292 udelay(5);
1293 }
1294
1295 /* Make sure (redundant) we've released our request to stay awake */
1296 iwl_clear_bit(trans, CSR_GP_CNTRL,
1297 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1298
1299 /* Stop the device, and put it in low power state */
1300 iwl_apm_stop(trans);
1301
1302 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1303 * Clean again the interrupt here
1304 */
1305 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1306 iwl_disable_interrupts(trans);
1307 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1308
1309 /* wait to make sure we flush pending tasklet*/
1310 synchronize_irq(trans_pcie->irq);
1311 tasklet_kill(&trans_pcie->irq_tasklet);
1312
1313 cancel_work_sync(&trans_pcie->rx_replenish);
1314
1315 /* stop and reset the on-board processor */
1316 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1317 }
1318
iwl_trans_pcie_wowlan_suspend(struct iwl_trans * trans)1319 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1320 {
1321 /* let the ucode operate on its own */
1322 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1323 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1324
1325 iwl_disable_interrupts(trans);
1326 iwl_clear_bit(trans, CSR_GP_CNTRL,
1327 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1328 }
1329
iwl_trans_pcie_tx(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_device_cmd * dev_cmd,enum iwl_rxon_context_id ctx,u8 sta_id,u8 tid)1330 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1331 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1332 u8 sta_id, u8 tid)
1333 {
1334 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1335 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1336 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1337 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1338 struct iwl_cmd_meta *out_meta;
1339 struct iwl_tx_queue *txq;
1340 struct iwl_queue *q;
1341
1342 dma_addr_t phys_addr = 0;
1343 dma_addr_t txcmd_phys;
1344 dma_addr_t scratch_phys;
1345 u16 len, firstlen, secondlen;
1346 u8 wait_write_ptr = 0;
1347 u8 txq_id;
1348 bool is_agg = false;
1349 __le16 fc = hdr->frame_control;
1350 u8 hdr_len = ieee80211_hdrlen(fc);
1351 u16 __maybe_unused wifi_seq;
1352
1353 /*
1354 * Send this frame after DTIM -- there's a special queue
1355 * reserved for this for contexts that support AP mode.
1356 */
1357 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1358 txq_id = trans_pcie->mcast_queue[ctx];
1359
1360 /*
1361 * The microcode will clear the more data
1362 * bit in the last frame it transmits.
1363 */
1364 hdr->frame_control |=
1365 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1366 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1367 txq_id = IWL_AUX_QUEUE;
1368 else
1369 txq_id =
1370 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1371
1372 /* aggregation is on for this <sta,tid> */
1373 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1374 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1375 txq_id = trans_pcie->agg_txq[sta_id][tid];
1376 is_agg = true;
1377 }
1378
1379 txq = &trans_pcie->txq[txq_id];
1380 q = &txq->q;
1381
1382 spin_lock(&txq->lock);
1383
1384 /* In AGG mode, the index in the ring must correspond to the WiFi
1385 * sequence number. This is a HW requirements to help the SCD to parse
1386 * the BA.
1387 * Check here that the packets are in the right place on the ring.
1388 */
1389 #ifdef CONFIG_IWLWIFI_DEBUG
1390 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1391 WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1392 "Q: %d WiFi Seq %d tfdNum %d",
1393 txq_id, wifi_seq, q->write_ptr);
1394 #endif
1395
1396 /* Set up driver data for this TFD */
1397 txq->skbs[q->write_ptr] = skb;
1398 txq->cmd[q->write_ptr] = dev_cmd;
1399
1400 dev_cmd->hdr.cmd = REPLY_TX;
1401 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1402 INDEX_TO_SEQ(q->write_ptr)));
1403
1404 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1405 out_meta = &txq->meta[q->write_ptr];
1406
1407 /*
1408 * Use the first empty entry in this queue's command buffer array
1409 * to contain the Tx command and MAC header concatenated together
1410 * (payload data will be in another buffer).
1411 * Size of this varies, due to varying MAC header length.
1412 * If end is not dword aligned, we'll have 2 extra bytes at the end
1413 * of the MAC header (device reads on dword boundaries).
1414 * We'll tell device about this padding later.
1415 */
1416 len = sizeof(struct iwl_tx_cmd) +
1417 sizeof(struct iwl_cmd_header) + hdr_len;
1418 firstlen = (len + 3) & ~3;
1419
1420 /* Tell NIC about any 2-byte padding after MAC header */
1421 if (firstlen != len)
1422 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1423
1424 /* Physical address of this Tx command's header (not MAC header!),
1425 * within command buffer array. */
1426 txcmd_phys = dma_map_single(trans->dev,
1427 &dev_cmd->hdr, firstlen,
1428 DMA_BIDIRECTIONAL);
1429 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1430 goto out_err;
1431 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1432 dma_unmap_len_set(out_meta, len, firstlen);
1433
1434 if (!ieee80211_has_morefrags(fc)) {
1435 txq->need_update = 1;
1436 } else {
1437 wait_write_ptr = 1;
1438 txq->need_update = 0;
1439 }
1440
1441 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1442 * if any (802.11 null frames have no payload). */
1443 secondlen = skb->len - hdr_len;
1444 if (secondlen > 0) {
1445 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1446 secondlen, DMA_TO_DEVICE);
1447 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1448 dma_unmap_single(trans->dev,
1449 dma_unmap_addr(out_meta, mapping),
1450 dma_unmap_len(out_meta, len),
1451 DMA_BIDIRECTIONAL);
1452 goto out_err;
1453 }
1454 }
1455
1456 /* Attach buffers to TFD */
1457 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1458 if (secondlen > 0)
1459 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1460 secondlen, 0);
1461
1462 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1463 offsetof(struct iwl_tx_cmd, scratch);
1464
1465 /* take back ownership of DMA buffer to enable update */
1466 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1467 DMA_BIDIRECTIONAL);
1468 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1469 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1470
1471 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1472 le16_to_cpu(dev_cmd->hdr.sequence));
1473 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1474
1475 /* Set up entry for this TFD in Tx byte-count array */
1476 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1477
1478 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1479 DMA_BIDIRECTIONAL);
1480
1481 trace_iwlwifi_dev_tx(trans->dev,
1482 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1483 sizeof(struct iwl_tfd),
1484 &dev_cmd->hdr, firstlen,
1485 skb->data + hdr_len, secondlen);
1486
1487 /* Tell device the write index *just past* this latest filled TFD */
1488 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1489 iwl_txq_update_write_ptr(trans, txq);
1490
1491 /*
1492 * At this point the frame is "transmitted" successfully
1493 * and we will get a TX status notification eventually,
1494 * regardless of the value of ret. "ret" only indicates
1495 * whether or not we should update the write pointer.
1496 */
1497 if (iwl_queue_space(q) < q->high_mark) {
1498 if (wait_write_ptr) {
1499 txq->need_update = 1;
1500 iwl_txq_update_write_ptr(trans, txq);
1501 } else {
1502 iwl_stop_queue(trans, txq);
1503 }
1504 }
1505 spin_unlock(&txq->lock);
1506 return 0;
1507 out_err:
1508 spin_unlock(&txq->lock);
1509 return -1;
1510 }
1511
iwl_trans_pcie_start_hw(struct iwl_trans * trans)1512 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1513 {
1514 struct iwl_trans_pcie *trans_pcie =
1515 IWL_TRANS_GET_PCIE_TRANS(trans);
1516 int err;
1517 bool hw_rfkill;
1518
1519 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1520
1521 if (!trans_pcie->irq_requested) {
1522 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1523 iwl_irq_tasklet, (unsigned long)trans);
1524
1525 iwl_alloc_isr_ict(trans);
1526
1527 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1528 DRV_NAME, trans);
1529 if (err) {
1530 IWL_ERR(trans, "Error allocating IRQ %d\n",
1531 trans_pcie->irq);
1532 goto error;
1533 }
1534
1535 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1536 trans_pcie->irq_requested = true;
1537 }
1538
1539 err = iwl_prepare_card_hw(trans);
1540 if (err) {
1541 IWL_ERR(trans, "Error while preparing HW: %d", err);
1542 goto err_free_irq;
1543 }
1544
1545 iwl_apm_init(trans);
1546
1547 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1548 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1549 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1550
1551 return err;
1552
1553 err_free_irq:
1554 free_irq(trans_pcie->irq, trans);
1555 error:
1556 iwl_free_isr_ict(trans);
1557 tasklet_kill(&trans_pcie->irq_tasklet);
1558 return err;
1559 }
1560
iwl_trans_pcie_stop_hw(struct iwl_trans * trans)1561 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1562 {
1563 iwl_apm_stop(trans);
1564
1565 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1566
1567 /* Even if we stop the HW, we still want the RF kill interrupt */
1568 iwl_enable_rfkill_int(trans);
1569 }
1570
iwl_trans_pcie_reclaim(struct iwl_trans * trans,int sta_id,int tid,int txq_id,int ssn,struct sk_buff_head * skbs)1571 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1572 int txq_id, int ssn, struct sk_buff_head *skbs)
1573 {
1574 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1575 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1576 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1577 int tfd_num = ssn & (txq->q.n_bd - 1);
1578 int freed = 0;
1579
1580 spin_lock(&txq->lock);
1581
1582 txq->time_stamp = jiffies;
1583
1584 if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1585 tid != IWL_TID_NON_QOS &&
1586 txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1587 /*
1588 * FIXME: this is a uCode bug which need to be addressed,
1589 * log the information and return for now.
1590 * Since it is can possibly happen very often and in order
1591 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1592 */
1593 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1594 "agg_txq[sta_id[tid] %d", txq_id,
1595 trans_pcie->agg_txq[sta_id][tid]);
1596 spin_unlock(&txq->lock);
1597 return 1;
1598 }
1599
1600 if (txq->q.read_ptr != tfd_num) {
1601 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1602 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1603 tfd_num, ssn);
1604 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1605 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1606 iwl_wake_queue(trans, txq);
1607 }
1608
1609 spin_unlock(&txq->lock);
1610 return 0;
1611 }
1612
iwl_trans_pcie_write8(struct iwl_trans * trans,u32 ofs,u8 val)1613 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1614 {
1615 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1616 }
1617
iwl_trans_pcie_write32(struct iwl_trans * trans,u32 ofs,u32 val)1618 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1619 {
1620 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1621 }
1622
iwl_trans_pcie_read32(struct iwl_trans * trans,u32 ofs)1623 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1624 {
1625 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1626 }
1627
iwl_trans_pcie_configure(struct iwl_trans * trans,const struct iwl_trans_config * trans_cfg)1628 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1629 const struct iwl_trans_config *trans_cfg)
1630 {
1631 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1632
1633 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1634 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1635 trans_pcie->n_no_reclaim_cmds = 0;
1636 else
1637 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1638 if (trans_pcie->n_no_reclaim_cmds)
1639 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1640 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1641 }
1642
iwl_trans_pcie_free(struct iwl_trans * trans)1643 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1644 {
1645 struct iwl_trans_pcie *trans_pcie =
1646 IWL_TRANS_GET_PCIE_TRANS(trans);
1647
1648 iwl_trans_pcie_tx_free(trans);
1649 #ifndef CONFIG_IWLWIFI_IDI
1650 iwl_trans_pcie_rx_free(trans);
1651 #endif
1652 if (trans_pcie->irq_requested == true) {
1653 free_irq(trans_pcie->irq, trans);
1654 iwl_free_isr_ict(trans);
1655 }
1656
1657 pci_disable_msi(trans_pcie->pci_dev);
1658 iounmap(trans_pcie->hw_base);
1659 pci_release_regions(trans_pcie->pci_dev);
1660 pci_disable_device(trans_pcie->pci_dev);
1661
1662 trans->shrd->trans = NULL;
1663 kfree(trans);
1664 }
1665
1666 #ifdef CONFIG_PM_SLEEP
iwl_trans_pcie_suspend(struct iwl_trans * trans)1667 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1668 {
1669 return 0;
1670 }
1671
iwl_trans_pcie_resume(struct iwl_trans * trans)1672 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1673 {
1674 bool hw_rfkill;
1675
1676 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1677 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1678
1679 if (hw_rfkill)
1680 iwl_enable_rfkill_int(trans);
1681 else
1682 iwl_enable_interrupts(trans);
1683
1684 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1685
1686 return 0;
1687 }
1688 #endif /* CONFIG_PM_SLEEP */
1689
1690 #define IWL_FLUSH_WAIT_MS 2000
1691
iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans * trans)1692 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1693 {
1694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1695 struct iwl_tx_queue *txq;
1696 struct iwl_queue *q;
1697 int cnt;
1698 unsigned long now = jiffies;
1699 int ret = 0;
1700
1701 /* waiting for all the tx frames complete might take a while */
1702 for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
1703 if (cnt == trans_pcie->cmd_queue)
1704 continue;
1705 txq = &trans_pcie->txq[cnt];
1706 q = &txq->q;
1707 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1708 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1709 msleep(1);
1710
1711 if (q->read_ptr != q->write_ptr) {
1712 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1713 ret = -ETIMEDOUT;
1714 break;
1715 }
1716 }
1717 return ret;
1718 }
1719
1720 /*
1721 * On every watchdog tick we check (latest) time stamp. If it does not
1722 * change during timeout period and queue is not empty we reset firmware.
1723 */
iwl_trans_pcie_check_stuck_queue(struct iwl_trans * trans,int cnt)1724 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1725 {
1726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1727 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1728 struct iwl_queue *q = &txq->q;
1729 unsigned long timeout;
1730
1731 if (q->read_ptr == q->write_ptr) {
1732 txq->time_stamp = jiffies;
1733 return 0;
1734 }
1735
1736 timeout = txq->time_stamp +
1737 msecs_to_jiffies(hw_params(trans).wd_timeout);
1738
1739 if (time_after(jiffies, timeout)) {
1740 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1741 hw_params(trans).wd_timeout);
1742 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1743 q->read_ptr, q->write_ptr);
1744 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1745 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1746 & (TFD_QUEUE_SIZE_MAX - 1),
1747 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1748 return 1;
1749 }
1750
1751 return 0;
1752 }
1753
get_fh_string(int cmd)1754 static const char *get_fh_string(int cmd)
1755 {
1756 switch (cmd) {
1757 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1758 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1759 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1760 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1761 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1762 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1763 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1764 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1765 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1766 default:
1767 return "UNKNOWN";
1768 }
1769 }
1770
iwl_dump_fh(struct iwl_trans * trans,char ** buf)1771 int iwl_dump_fh(struct iwl_trans *trans, char **buf)
1772 {
1773 int i;
1774 static const u32 fh_tbl[] = {
1775 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1776 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1777 FH_RSCSR_CHNL0_WPTR,
1778 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1779 FH_MEM_RSSR_SHARED_CTRL_REG,
1780 FH_MEM_RSSR_RX_STATUS_REG,
1781 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1782 FH_TSSR_TX_STATUS_REG,
1783 FH_TSSR_TX_ERROR_REG
1784 };
1785
1786 #ifdef CONFIG_IWLWIFI_DEBUGFS
1787 if (buf) {
1788 int pos = 0;
1789 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1790
1791 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1792 *buf = kmalloc(bufsz, GFP_KERNEL);
1793 if (!*buf)
1794 return -ENOMEM;
1795 pos += scnprintf(*buf + pos, bufsz - pos,
1796 "FH register values:\n");
1797
1798 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1799 pos += scnprintf(*buf + pos, bufsz - pos,
1800 " %34s: 0X%08x\n",
1801 get_fh_string(fh_tbl[i]),
1802 iwl_read_direct32(trans, fh_tbl[i]));
1803
1804 return pos;
1805 }
1806 #endif
1807 IWL_ERR(trans, "FH register values:\n");
1808 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1809 IWL_ERR(trans, " %34s: 0X%08x\n",
1810 get_fh_string(fh_tbl[i]),
1811 iwl_read_direct32(trans, fh_tbl[i]));
1812
1813 return 0;
1814 }
1815
get_csr_string(int cmd)1816 static const char *get_csr_string(int cmd)
1817 {
1818 switch (cmd) {
1819 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1820 IWL_CMD(CSR_INT_COALESCING);
1821 IWL_CMD(CSR_INT);
1822 IWL_CMD(CSR_INT_MASK);
1823 IWL_CMD(CSR_FH_INT_STATUS);
1824 IWL_CMD(CSR_GPIO_IN);
1825 IWL_CMD(CSR_RESET);
1826 IWL_CMD(CSR_GP_CNTRL);
1827 IWL_CMD(CSR_HW_REV);
1828 IWL_CMD(CSR_EEPROM_REG);
1829 IWL_CMD(CSR_EEPROM_GP);
1830 IWL_CMD(CSR_OTP_GP_REG);
1831 IWL_CMD(CSR_GIO_REG);
1832 IWL_CMD(CSR_GP_UCODE_REG);
1833 IWL_CMD(CSR_GP_DRIVER_REG);
1834 IWL_CMD(CSR_UCODE_DRV_GP1);
1835 IWL_CMD(CSR_UCODE_DRV_GP2);
1836 IWL_CMD(CSR_LED_REG);
1837 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1838 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1839 IWL_CMD(CSR_ANA_PLL_CFG);
1840 IWL_CMD(CSR_HW_REV_WA_REG);
1841 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1842 default:
1843 return "UNKNOWN";
1844 }
1845 }
1846
iwl_dump_csr(struct iwl_trans * trans)1847 void iwl_dump_csr(struct iwl_trans *trans)
1848 {
1849 int i;
1850 static const u32 csr_tbl[] = {
1851 CSR_HW_IF_CONFIG_REG,
1852 CSR_INT_COALESCING,
1853 CSR_INT,
1854 CSR_INT_MASK,
1855 CSR_FH_INT_STATUS,
1856 CSR_GPIO_IN,
1857 CSR_RESET,
1858 CSR_GP_CNTRL,
1859 CSR_HW_REV,
1860 CSR_EEPROM_REG,
1861 CSR_EEPROM_GP,
1862 CSR_OTP_GP_REG,
1863 CSR_GIO_REG,
1864 CSR_GP_UCODE_REG,
1865 CSR_GP_DRIVER_REG,
1866 CSR_UCODE_DRV_GP1,
1867 CSR_UCODE_DRV_GP2,
1868 CSR_LED_REG,
1869 CSR_DRAM_INT_TBL_REG,
1870 CSR_GIO_CHICKEN_BITS,
1871 CSR_ANA_PLL_CFG,
1872 CSR_HW_REV_WA_REG,
1873 CSR_DBG_HPET_MEM_REG
1874 };
1875 IWL_ERR(trans, "CSR values:\n");
1876 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1877 "CSR_INT_PERIODIC_REG)\n");
1878 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1879 IWL_ERR(trans, " %25s: 0X%08x\n",
1880 get_csr_string(csr_tbl[i]),
1881 iwl_read32(trans, csr_tbl[i]));
1882 }
1883 }
1884
1885 #ifdef CONFIG_IWLWIFI_DEBUGFS
1886 /* create and remove of files */
1887 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1888 if (!debugfs_create_file(#name, mode, parent, trans, \
1889 &iwl_dbgfs_##name##_ops)) \
1890 return -ENOMEM; \
1891 } while (0)
1892
1893 /* file operation */
1894 #define DEBUGFS_READ_FUNC(name) \
1895 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1896 char __user *user_buf, \
1897 size_t count, loff_t *ppos);
1898
1899 #define DEBUGFS_WRITE_FUNC(name) \
1900 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1901 const char __user *user_buf, \
1902 size_t count, loff_t *ppos);
1903
1904
1905 #define DEBUGFS_READ_FILE_OPS(name) \
1906 DEBUGFS_READ_FUNC(name); \
1907 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1908 .read = iwl_dbgfs_##name##_read, \
1909 .open = simple_open, \
1910 .llseek = generic_file_llseek, \
1911 };
1912
1913 #define DEBUGFS_WRITE_FILE_OPS(name) \
1914 DEBUGFS_WRITE_FUNC(name); \
1915 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1916 .write = iwl_dbgfs_##name##_write, \
1917 .open = simple_open, \
1918 .llseek = generic_file_llseek, \
1919 };
1920
1921 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1922 DEBUGFS_READ_FUNC(name); \
1923 DEBUGFS_WRITE_FUNC(name); \
1924 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1925 .write = iwl_dbgfs_##name##_write, \
1926 .read = iwl_dbgfs_##name##_read, \
1927 .open = simple_open, \
1928 .llseek = generic_file_llseek, \
1929 };
1930
iwl_dbgfs_tx_queue_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)1931 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1932 char __user *user_buf,
1933 size_t count, loff_t *ppos)
1934 {
1935 struct iwl_trans *trans = file->private_data;
1936 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1937 struct iwl_tx_queue *txq;
1938 struct iwl_queue *q;
1939 char *buf;
1940 int pos = 0;
1941 int cnt;
1942 int ret;
1943 size_t bufsz;
1944
1945 bufsz = sizeof(char) * 64 * cfg(trans)->base_params->num_of_queues;
1946
1947 if (!trans_pcie->txq) {
1948 IWL_ERR(trans, "txq not ready\n");
1949 return -EAGAIN;
1950 }
1951 buf = kzalloc(bufsz, GFP_KERNEL);
1952 if (!buf)
1953 return -ENOMEM;
1954
1955 for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
1956 txq = &trans_pcie->txq[cnt];
1957 q = &txq->q;
1958 pos += scnprintf(buf + pos, bufsz - pos,
1959 "hwq %.2d: read=%u write=%u stop=%d"
1960 " swq_id=%#.2x (ac %d/hwq %d)\n",
1961 cnt, q->read_ptr, q->write_ptr,
1962 !!test_bit(cnt, trans_pcie->queue_stopped),
1963 txq->swq_id, txq->swq_id & 3,
1964 (txq->swq_id >> 2) & 0x1f);
1965 if (cnt >= 4)
1966 continue;
1967 /* for the ACs, display the stop count too */
1968 pos += scnprintf(buf + pos, bufsz - pos,
1969 " stop-count: %d\n",
1970 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1971 }
1972 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1973 kfree(buf);
1974 return ret;
1975 }
1976
iwl_dbgfs_rx_queue_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)1977 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1978 char __user *user_buf,
1979 size_t count, loff_t *ppos) {
1980 struct iwl_trans *trans = file->private_data;
1981 struct iwl_trans_pcie *trans_pcie =
1982 IWL_TRANS_GET_PCIE_TRANS(trans);
1983 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1984 char buf[256];
1985 int pos = 0;
1986 const size_t bufsz = sizeof(buf);
1987
1988 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1989 rxq->read);
1990 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1991 rxq->write);
1992 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1993 rxq->free_count);
1994 if (rxq->rb_stts) {
1995 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1996 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1997 } else {
1998 pos += scnprintf(buf + pos, bufsz - pos,
1999 "closed_rb_num: Not Allocated\n");
2000 }
2001 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2002 }
2003
2004 #ifdef CONFIG_IWLWIFI_DEBUG
iwl_dbgfs_log_event_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2005 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
2006 char __user *user_buf,
2007 size_t count, loff_t *ppos)
2008 {
2009 struct iwl_trans *trans = file->private_data;
2010 char *buf;
2011 int pos = 0;
2012 ssize_t ret = -ENOMEM;
2013
2014 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
2015 if (buf) {
2016 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2017 kfree(buf);
2018 }
2019 return ret;
2020 }
2021
iwl_dbgfs_log_event_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2022 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
2023 const char __user *user_buf,
2024 size_t count, loff_t *ppos)
2025 {
2026 struct iwl_trans *trans = file->private_data;
2027 u32 event_log_flag;
2028 char buf[8];
2029 int buf_size;
2030
2031 memset(buf, 0, sizeof(buf));
2032 buf_size = min(count, sizeof(buf) - 1);
2033 if (copy_from_user(buf, user_buf, buf_size))
2034 return -EFAULT;
2035 if (sscanf(buf, "%d", &event_log_flag) != 1)
2036 return -EFAULT;
2037 if (event_log_flag == 1)
2038 iwl_dump_nic_event_log(trans, true, NULL, false);
2039
2040 return count;
2041 }
2042 #endif
2043
iwl_dbgfs_interrupt_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2044 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2045 char __user *user_buf,
2046 size_t count, loff_t *ppos) {
2047
2048 struct iwl_trans *trans = file->private_data;
2049 struct iwl_trans_pcie *trans_pcie =
2050 IWL_TRANS_GET_PCIE_TRANS(trans);
2051 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2052
2053 int pos = 0;
2054 char *buf;
2055 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2056 ssize_t ret;
2057
2058 buf = kzalloc(bufsz, GFP_KERNEL);
2059 if (!buf) {
2060 IWL_ERR(trans, "Can not allocate Buffer\n");
2061 return -ENOMEM;
2062 }
2063
2064 pos += scnprintf(buf + pos, bufsz - pos,
2065 "Interrupt Statistics Report:\n");
2066
2067 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2068 isr_stats->hw);
2069 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2070 isr_stats->sw);
2071 if (isr_stats->sw || isr_stats->hw) {
2072 pos += scnprintf(buf + pos, bufsz - pos,
2073 "\tLast Restarting Code: 0x%X\n",
2074 isr_stats->err_code);
2075 }
2076 #ifdef CONFIG_IWLWIFI_DEBUG
2077 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2078 isr_stats->sch);
2079 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2080 isr_stats->alive);
2081 #endif
2082 pos += scnprintf(buf + pos, bufsz - pos,
2083 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2084
2085 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2086 isr_stats->ctkill);
2087
2088 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2089 isr_stats->wakeup);
2090
2091 pos += scnprintf(buf + pos, bufsz - pos,
2092 "Rx command responses:\t\t %u\n", isr_stats->rx);
2093
2094 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2095 isr_stats->tx);
2096
2097 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2098 isr_stats->unhandled);
2099
2100 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2101 kfree(buf);
2102 return ret;
2103 }
2104
iwl_dbgfs_interrupt_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2105 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2106 const char __user *user_buf,
2107 size_t count, loff_t *ppos)
2108 {
2109 struct iwl_trans *trans = file->private_data;
2110 struct iwl_trans_pcie *trans_pcie =
2111 IWL_TRANS_GET_PCIE_TRANS(trans);
2112 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2113
2114 char buf[8];
2115 int buf_size;
2116 u32 reset_flag;
2117
2118 memset(buf, 0, sizeof(buf));
2119 buf_size = min(count, sizeof(buf) - 1);
2120 if (copy_from_user(buf, user_buf, buf_size))
2121 return -EFAULT;
2122 if (sscanf(buf, "%x", &reset_flag) != 1)
2123 return -EFAULT;
2124 if (reset_flag == 0)
2125 memset(isr_stats, 0, sizeof(*isr_stats));
2126
2127 return count;
2128 }
2129
iwl_dbgfs_csr_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2130 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2131 const char __user *user_buf,
2132 size_t count, loff_t *ppos)
2133 {
2134 struct iwl_trans *trans = file->private_data;
2135 char buf[8];
2136 int buf_size;
2137 int csr;
2138
2139 memset(buf, 0, sizeof(buf));
2140 buf_size = min(count, sizeof(buf) - 1);
2141 if (copy_from_user(buf, user_buf, buf_size))
2142 return -EFAULT;
2143 if (sscanf(buf, "%d", &csr) != 1)
2144 return -EFAULT;
2145
2146 iwl_dump_csr(trans);
2147
2148 return count;
2149 }
2150
iwl_dbgfs_fh_reg_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2151 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2152 char __user *user_buf,
2153 size_t count, loff_t *ppos)
2154 {
2155 struct iwl_trans *trans = file->private_data;
2156 char *buf = NULL;
2157 int pos = 0;
2158 ssize_t ret = -EFAULT;
2159
2160 ret = pos = iwl_dump_fh(trans, &buf);
2161 if (buf) {
2162 ret = simple_read_from_buffer(user_buf,
2163 count, ppos, buf, pos);
2164 kfree(buf);
2165 }
2166
2167 return ret;
2168 }
2169
2170 #ifdef CONFIG_IWLWIFI_DEBUG
2171 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2172 #endif
2173 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2174 DEBUGFS_READ_FILE_OPS(fh_reg);
2175 DEBUGFS_READ_FILE_OPS(rx_queue);
2176 DEBUGFS_READ_FILE_OPS(tx_queue);
2177 DEBUGFS_WRITE_FILE_OPS(csr);
2178
2179 /*
2180 * Create the debugfs files and directories
2181 *
2182 */
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans,struct dentry * dir)2183 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2184 struct dentry *dir)
2185 {
2186 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2187 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2188 #ifdef CONFIG_IWLWIFI_DEBUG
2189 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2190 #endif
2191 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2192 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2193 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2194 return 0;
2195 }
2196 #else
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans,struct dentry * dir)2197 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2198 struct dentry *dir)
2199 { return 0; }
2200
2201 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2202
2203 const struct iwl_trans_ops trans_ops_pcie = {
2204 .start_hw = iwl_trans_pcie_start_hw,
2205 .stop_hw = iwl_trans_pcie_stop_hw,
2206 .fw_alive = iwl_trans_pcie_fw_alive,
2207 .start_fw = iwl_trans_pcie_start_fw,
2208 .stop_device = iwl_trans_pcie_stop_device,
2209
2210 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2211
2212 .send_cmd = iwl_trans_pcie_send_cmd,
2213
2214 .tx = iwl_trans_pcie_tx,
2215 .reclaim = iwl_trans_pcie_reclaim,
2216
2217 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2218 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2219 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2220
2221 .free = iwl_trans_pcie_free,
2222
2223 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2224
2225 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2226 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2227
2228 #ifdef CONFIG_PM_SLEEP
2229 .suspend = iwl_trans_pcie_suspend,
2230 .resume = iwl_trans_pcie_resume,
2231 #endif
2232 .write8 = iwl_trans_pcie_write8,
2233 .write32 = iwl_trans_pcie_write32,
2234 .read32 = iwl_trans_pcie_read32,
2235 .configure = iwl_trans_pcie_configure,
2236 };
2237
iwl_trans_pcie_alloc(struct iwl_shared * shrd,struct pci_dev * pdev,const struct pci_device_id * ent)2238 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2239 struct pci_dev *pdev,
2240 const struct pci_device_id *ent)
2241 {
2242 struct iwl_trans_pcie *trans_pcie;
2243 struct iwl_trans *trans;
2244 u16 pci_cmd;
2245 int err;
2246
2247 trans = kzalloc(sizeof(struct iwl_trans) +
2248 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2249
2250 if (WARN_ON(!trans))
2251 return NULL;
2252
2253 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2254
2255 trans->ops = &trans_ops_pcie;
2256 trans->shrd = shrd;
2257 trans_pcie->trans = trans;
2258 spin_lock_init(&trans_pcie->irq_lock);
2259 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2260
2261 /* W/A - seems to solve weird behavior. We need to remove this if we
2262 * don't want to stay in L1 all the time. This wastes a lot of power */
2263 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2264 PCIE_LINK_STATE_CLKPM);
2265
2266 if (pci_enable_device(pdev)) {
2267 err = -ENODEV;
2268 goto out_no_pci;
2269 }
2270
2271 pci_set_master(pdev);
2272
2273 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2274 if (!err)
2275 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2276 if (err) {
2277 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2278 if (!err)
2279 err = pci_set_consistent_dma_mask(pdev,
2280 DMA_BIT_MASK(32));
2281 /* both attempts failed: */
2282 if (err) {
2283 dev_printk(KERN_ERR, &pdev->dev,
2284 "No suitable DMA available.\n");
2285 goto out_pci_disable_device;
2286 }
2287 }
2288
2289 err = pci_request_regions(pdev, DRV_NAME);
2290 if (err) {
2291 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2292 goto out_pci_disable_device;
2293 }
2294
2295 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2296 if (!trans_pcie->hw_base) {
2297 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2298 err = -ENODEV;
2299 goto out_pci_release_regions;
2300 }
2301
2302 dev_printk(KERN_INFO, &pdev->dev,
2303 "pci_resource_len = 0x%08llx\n",
2304 (unsigned long long) pci_resource_len(pdev, 0));
2305 dev_printk(KERN_INFO, &pdev->dev,
2306 "pci_resource_base = %p\n", trans_pcie->hw_base);
2307
2308 dev_printk(KERN_INFO, &pdev->dev,
2309 "HW Revision ID = 0x%X\n", pdev->revision);
2310
2311 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2312 * PCI Tx retries from interfering with C3 CPU state */
2313 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2314
2315 err = pci_enable_msi(pdev);
2316 if (err)
2317 dev_printk(KERN_ERR, &pdev->dev,
2318 "pci_enable_msi failed(0X%x)", err);
2319
2320 trans->dev = &pdev->dev;
2321 trans_pcie->irq = pdev->irq;
2322 trans_pcie->pci_dev = pdev;
2323 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2324 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2325 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2326 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2327
2328 /* TODO: Move this away, not needed if not MSI */
2329 /* enable rfkill interrupt: hw bug w/a */
2330 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2331 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2332 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2333 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2334 }
2335
2336 /* Initialize the wait queue for commands */
2337 init_waitqueue_head(&trans->wait_command_queue);
2338
2339 return trans;
2340
2341 out_pci_release_regions:
2342 pci_release_regions(pdev);
2343 out_pci_disable_device:
2344 pci_disable_device(pdev);
2345 out_no_pci:
2346 kfree(trans);
2347 return NULL;
2348 }
2349
2350