1 /*
2 * linux/arch/arm/mach-omap1/irq.c
3 *
4 * Interrupt handler for all OMAP boards
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
9 *
10 * Completely re-written to support various OMAP chips with bank specific
11 * interrupt handlers.
12 *
13 * Some snippets of the code taken from the older OMAP interrupt handler
14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
15 *
16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38 #include <linux/gpio.h>
39 #include <linux/init.h>
40 #include <linux/module.h>
41 #include <linux/sched.h>
42 #include <linux/interrupt.h>
43 #include <linux/io.h>
44
45 #include <asm/irq.h>
46 #include <asm/mach/irq.h>
47
48 #include <plat/cpu.h>
49
50 #include <mach/hardware.h>
51
52 #define IRQ_BANK(irq) ((irq) >> 5)
53 #define IRQ_BIT(irq) ((irq) & 0x1f)
54
55 struct omap_irq_bank {
56 unsigned long base_reg;
57 unsigned long trigger_map;
58 unsigned long wake_enable;
59 };
60
61 u32 omap_irq_flags;
62 static unsigned int irq_bank_count;
63 static struct omap_irq_bank *irq_banks;
64
irq_bank_readl(int bank,int offset)65 static inline unsigned int irq_bank_readl(int bank, int offset)
66 {
67 return omap_readl(irq_banks[bank].base_reg + offset);
68 }
69
irq_bank_writel(unsigned long value,int bank,int offset)70 static inline void irq_bank_writel(unsigned long value, int bank, int offset)
71 {
72 omap_writel(value, irq_banks[bank].base_reg + offset);
73 }
74
omap_ack_irq(struct irq_data * d)75 static void omap_ack_irq(struct irq_data *d)
76 {
77 if (d->irq > 31)
78 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
79
80 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
81 }
82
omap_mask_irq(struct irq_data * d)83 static void omap_mask_irq(struct irq_data *d)
84 {
85 int bank = IRQ_BANK(d->irq);
86 u32 l;
87
88 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
89 l |= 1 << IRQ_BIT(d->irq);
90 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
91 }
92
omap_unmask_irq(struct irq_data * d)93 static void omap_unmask_irq(struct irq_data *d)
94 {
95 int bank = IRQ_BANK(d->irq);
96 u32 l;
97
98 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
99 l &= ~(1 << IRQ_BIT(d->irq));
100 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
101 }
102
omap_mask_ack_irq(struct irq_data * d)103 static void omap_mask_ack_irq(struct irq_data *d)
104 {
105 omap_mask_irq(d);
106 omap_ack_irq(d);
107 }
108
omap_wake_irq(struct irq_data * d,unsigned int enable)109 static int omap_wake_irq(struct irq_data *d, unsigned int enable)
110 {
111 int bank = IRQ_BANK(d->irq);
112
113 if (enable)
114 irq_banks[bank].wake_enable |= IRQ_BIT(d->irq);
115 else
116 irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq);
117
118 return 0;
119 }
120
121
122 /*
123 * Allows tuning the IRQ type and priority
124 *
125 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
126 * mailing list threads on FIQ handlers if you are planning to
127 * add a FIQ handler for OMAP.
128 */
omap_irq_set_cfg(int irq,int fiq,int priority,int trigger)129 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
130 {
131 signed int bank;
132 unsigned long val, offset;
133
134 bank = IRQ_BANK(irq);
135 /* FIQ is only available on bank 0 interrupts */
136 fiq = bank ? 0 : (fiq & 0x1);
137 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
138 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
139 irq_bank_writel(val, bank, offset);
140 }
141
142 #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
143 static struct omap_irq_bank omap7xx_irq_banks[] = {
144 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
145 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
146 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
147 };
148 #endif
149
150 #ifdef CONFIG_ARCH_OMAP15XX
151 static struct omap_irq_bank omap1510_irq_banks[] = {
152 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
153 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
154 };
155 static struct omap_irq_bank omap310_irq_banks[] = {
156 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
157 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
158 };
159 #endif
160
161 #if defined(CONFIG_ARCH_OMAP16XX)
162
163 static struct omap_irq_bank omap1610_irq_banks[] = {
164 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
165 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
166 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
167 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
168 };
169 #endif
170
171 static struct irq_chip omap_irq_chip = {
172 .name = "MPU",
173 .irq_ack = omap_mask_ack_irq,
174 .irq_mask = omap_mask_irq,
175 .irq_unmask = omap_unmask_irq,
176 .irq_set_wake = omap_wake_irq,
177 };
178
omap1_init_irq(void)179 void __init omap1_init_irq(void)
180 {
181 int i, j;
182
183 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
184 if (cpu_is_omap7xx()) {
185 omap_irq_flags = INT_7XX_IH2_IRQ;
186 irq_banks = omap7xx_irq_banks;
187 irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
188 }
189 #endif
190 #ifdef CONFIG_ARCH_OMAP15XX
191 if (cpu_is_omap1510()) {
192 omap_irq_flags = INT_1510_IH2_IRQ;
193 irq_banks = omap1510_irq_banks;
194 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
195 }
196 if (cpu_is_omap310()) {
197 omap_irq_flags = INT_1510_IH2_IRQ;
198 irq_banks = omap310_irq_banks;
199 irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
200 }
201 #endif
202 #if defined(CONFIG_ARCH_OMAP16XX)
203 if (cpu_is_omap16xx()) {
204 omap_irq_flags = INT_1510_IH2_IRQ;
205 irq_banks = omap1610_irq_banks;
206 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
207 }
208 #endif
209 printk("Total of %i interrupts in %i interrupt banks\n",
210 irq_bank_count * 32, irq_bank_count);
211
212 /* Mask and clear all interrupts */
213 for (i = 0; i < irq_bank_count; i++) {
214 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
215 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
216 }
217
218 /* Clear any pending interrupts */
219 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
220 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
221
222 /* Enable interrupts in global mask */
223 if (cpu_is_omap7xx())
224 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
225
226 /* Install the interrupt handlers for each bank */
227 for (i = 0; i < irq_bank_count; i++) {
228 for (j = i * 32; j < (i + 1) * 32; j++) {
229 int irq_trigger;
230
231 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
232 omap_irq_set_cfg(j, 0, 0, irq_trigger);
233
234 irq_set_chip_and_handler(j, &omap_irq_chip,
235 handle_level_irq);
236 set_irq_flags(j, IRQF_VALID);
237 }
238 }
239
240 /* Unmask level 2 handler */
241
242 if (cpu_is_omap7xx())
243 omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ));
244 else if (cpu_is_omap15xx())
245 omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ));
246 else if (cpu_is_omap16xx())
247 omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ));
248 }
249