Searched refs:iii (Results 1 – 18 of 18) sorted by relevance
90 #define RFV_SIGN(iii) (((iii) >> 2) & 0x3) argument91 #define RFV_SYM(iii) (((iii) >> 4) & 0x3) argument92 #define RFV_STK(iii) (((iii) >> 6) & 0x3) argument93 #define RFV_ACCS(iii) ((iii) & 0x3) argument96 #define RFV_SCALE(iii) ((iii) >> 11) argument97 #define RFV_BIGOFF(iii) (((iii) >> 8) & 0x7) argument99 #define RFV_BIGOFF(iii) ((iii) >> 8) argument
36 iii) PCI-SIG's I/O Virtualization79 iii)max_config_vpath
139 XFRM_MSG_NEWAE is also issued to any listeners as described in iii).146 iii) kernel->user to report as event if someone sets any values or
59 (iii) Intel will not provide or be required to assist in providing
72 (iii) Intel will not provide or be required to assist in providing
115 __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
61 iii) XOR Accelerator node
128 iii) ZMII node
56 rc-msi-digivox-iii.o \
19 iii. Implement any policy mechanisms in one place.
428 iii. Module compilation reorder in Makefile so that unresolved symbols do448 iii. Have extended wait when issuing command in synchronous mode. This is497 iii. Typo corrected for subsys id for megaraid sata 300-4x549 iii. Miscellaneous indentation and goto/label fixes.591 iii. Many fixes as suggested by Christoph Hellwig <hch@infradead.org> on
433 iii. megasas_ctrl_info struct reverted to 3.02 release455 iii. Frame count optimization. Main frame can contain 2 SGE for 64 bit SGLs and
195 iii) set the Layer 2 protocol to hdlc219 iii) then, after the Layer 2 protocol is set, set the encapsulation 244 iii) set the Layer 2 protocol to hdlc and the Layer 3 protocol to
257 iii) Xilinx EMAC and Xilinx TEMAC
225 iii. The i/o scheduler algorithm itself can be replaced/set as appropriate407 iii.Ability to represent large i/os w/o unnecessarily breaking them up (i.e1002 iii. [none]1012 iii. better utilization of h/w & CPU time1035 iii. Plugging the queue to batch requests in anticipation of opportunities for
260 iii) Messages
72 (iii) Kernel Interface
510 # (iii) (a7)+; divide-by-zero