1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved. 7 */ 8 9 #ifndef _ASM_IA64_SN_SHUBIO_H 10 #define _ASM_IA64_SN_SHUBIO_H 11 12 #define HUB_WIDGET_ID_MAX 0xf 13 #define IIO_NUM_ITTES 7 14 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) 15 16 #define IIO_WID 0x00400000 /* Crosstalk Widget Identification */ 17 /* This register is also accessible from 18 * Crosstalk at address 0x0. */ 19 #define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */ 20 #define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */ 21 #define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */ 22 #define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */ 23 #define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */ 24 #define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */ 25 #define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */ 26 #define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */ 27 #define IIO_ILLR 0x00400130 /* IO LLP Log Register */ 28 #define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */ 29 30 #define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */ 31 #define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */ 32 33 #define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */ 34 #define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */ 35 36 #define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */ 37 #define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */ 38 #define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */ 39 #define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */ 40 #define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */ 41 #define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */ 42 #define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */ 43 44 #define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ 45 #define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ 46 #define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ 47 #define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ 48 #define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ 49 #define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ 50 #define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ 51 #define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ 52 #define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ 53 54 #define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */ 55 #define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */ 56 #define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */ 57 #define IIO_IECLR 0x004001F8 /* IO Error Clear Register */ 58 #define IIO_IBCR 0x00400200 /* IO BTE Control Register */ 59 60 #define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */ 61 #define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */ 62 63 #define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ 64 65 #define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */ 66 #define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */ 67 68 #define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */ 69 #define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */ 70 71 #define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */ 72 #define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */ 73 #define IIO_IWC 0x00400250 /* IO Wrapper Control Register */ 74 #define IIO_IWS 0x00400258 /* IO Wrapper Status Register */ 75 #define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */ 76 77 #define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */ 78 79 #define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */ 80 #define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */ 81 #define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */ 82 #define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */ 83 #define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */ 84 #define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */ 85 #define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */ 86 #define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */ 87 88 #define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */ 89 #define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */ 90 #define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */ 91 #define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */ 92 #define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */ 93 #define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */ 94 #define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */ 95 #define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */ 96 97 #define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */ 98 #define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */ 99 #define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */ 100 #define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */ 101 #define IIO_ICMR 0x004003A8 /* IO CRB Management Register */ 102 #define IIO_ICCR 0x004003B0 /* IO CRB Control Register */ 103 #define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ 104 #define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */ 105 106 #define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ 107 #define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ 108 #define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ 109 #define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ 110 #define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */ 111 112 #define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */ 113 #define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */ 114 #define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */ 115 #define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */ 116 #define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */ 117 118 #define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */ 119 #define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */ 120 #define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */ 121 #define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */ 122 #define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */ 123 124 #define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */ 125 #define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */ 126 #define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */ 127 #define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */ 128 #define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */ 129 130 #define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */ 131 #define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */ 132 #define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */ 133 #define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */ 134 #define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */ 135 136 #define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */ 137 #define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */ 138 #define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */ 139 #define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */ 140 #define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */ 141 142 #define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */ 143 #define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */ 144 #define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */ 145 #define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */ 146 #define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */ 147 148 #define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */ 149 #define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */ 150 #define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */ 151 #define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */ 152 #define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */ 153 154 #define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */ 155 #define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */ 156 #define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */ 157 #define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */ 158 #define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */ 159 160 #define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */ 161 #define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */ 162 #define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */ 163 #define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */ 164 #define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */ 165 166 #define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */ 167 #define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */ 168 #define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */ 169 #define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */ 170 #define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */ 171 172 #define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */ 173 #define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */ 174 #define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */ 175 #define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */ 176 #define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */ 177 178 #define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */ 179 #define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */ 180 #define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */ 181 #define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */ 182 #define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */ 183 184 #define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */ 185 #define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */ 186 #define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */ 187 #define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */ 188 #define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */ 189 190 #define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */ 191 #define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */ 192 #define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */ 193 #define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */ 194 #define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */ 195 196 #define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */ 197 #define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */ 198 #define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */ 199 200 #define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */ 201 202 #define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */ 203 #define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */ 204 #define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */ 205 #define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */ 206 #define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */ 207 #define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */ 208 #define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */ 209 #define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */ 210 #define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */ 211 #define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */ 212 #define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */ 213 #define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */ 214 215 #define IIO_IPCR 0x00430000 /* IO Performance Control */ 216 #define IIO_IPPR 0x00430008 /* IO Performance Profiling */ 217 218 /************************************************************************ 219 * * 220 * Description: This register echoes some information from the * 221 * LB_REV_ID register. It is available through Crosstalk as described * 222 * above. The REV_NUM and MFG_NUM fields receive their values from * 223 * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * 224 * The PART_NUM field's value is the Crosstalk device ID number that * 225 * Steve Miller assigned to the SHub chip. * 226 * * 227 ************************************************************************/ 228 229 typedef union ii_wid_u { 230 u64 ii_wid_regval; 231 struct { 232 u64 w_rsvd_1:1; 233 u64 w_mfg_num:11; 234 u64 w_part_num:16; 235 u64 w_rev_num:4; 236 u64 w_rsvd:32; 237 } ii_wid_fld_s; 238 } ii_wid_u_t; 239 240 /************************************************************************ 241 * * 242 * The fields in this register are set upon detection of an error * 243 * and cleared by various mechanisms, as explained in the * 244 * description. * 245 * * 246 ************************************************************************/ 247 248 typedef union ii_wstat_u { 249 u64 ii_wstat_regval; 250 struct { 251 u64 w_pending:4; 252 u64 w_xt_crd_to:1; 253 u64 w_xt_tail_to:1; 254 u64 w_rsvd_3:3; 255 u64 w_tx_mx_rty:1; 256 u64 w_rsvd_2:6; 257 u64 w_llp_tx_cnt:8; 258 u64 w_rsvd_1:8; 259 u64 w_crazy:1; 260 u64 w_rsvd:31; 261 } ii_wstat_fld_s; 262 } ii_wstat_u_t; 263 264 /************************************************************************ 265 * * 266 * Description: This is a read-write enabled register. It controls * 267 * various aspects of the Crosstalk flow control. * 268 * * 269 ************************************************************************/ 270 271 typedef union ii_wcr_u { 272 u64 ii_wcr_regval; 273 struct { 274 u64 w_wid:4; 275 u64 w_tag:1; 276 u64 w_rsvd_1:8; 277 u64 w_dst_crd:3; 278 u64 w_f_bad_pkt:1; 279 u64 w_dir_con:1; 280 u64 w_e_thresh:5; 281 u64 w_rsvd:41; 282 } ii_wcr_fld_s; 283 } ii_wcr_u_t; 284 285 /************************************************************************ 286 * * 287 * Description: This register's value is a bit vector that guards * 288 * access to local registers within the II as well as to external * 289 * Crosstalk widgets. Each bit in the register corresponds to a * 290 * particular region in the system; a region consists of one, two or * 291 * four nodes (depending on the value of the REGION_SIZE field in the * 292 * LB_REV_ID register, which is documented in Section 8.3.1.1). The * 293 * protection provided by this register applies to PIO read * 294 * operations as well as PIO write operations. The II will perform a * 295 * PIO read or write request only if the bit for the requestor's * 296 * region is set; otherwise, the II will not perform the requested * 297 * operation and will return an error response. When a PIO read or * 298 * write request targets an external Crosstalk widget, then not only * 299 * must the bit for the requestor's region be set in the ILAPR, but * 300 * also the target widget's bit in the IOWA register must be set in * 301 * order for the II to perform the requested operation; otherwise, * 302 * the II will return an error response. Hence, the protection * 303 * provided by the IOWA register supplements the protection provided * 304 * by the ILAPR for requests that target external Crosstalk widgets. * 305 * This register itself can be accessed only by the nodes whose * 306 * region ID bits are enabled in this same register. It can also be * 307 * accessed through the IAlias space by the local processors. * 308 * The reset value of this register allows access by all nodes. * 309 * * 310 ************************************************************************/ 311 312 typedef union ii_ilapr_u { 313 u64 ii_ilapr_regval; 314 struct { 315 u64 i_region:64; 316 } ii_ilapr_fld_s; 317 } ii_ilapr_u_t; 318 319 /************************************************************************ 320 * * 321 * Description: A write to this register of the 64-bit value * 322 * "SGIrules" in ASCII, will cause the bit in the ILAPR register * 323 * corresponding to the region of the requestor to be set (allow * 324 * access). A write of any other value will be ignored. Access * 325 * protection for this register is "SGIrules". * 326 * This register can also be accessed through the IAlias space. * 327 * However, this access will not change the access permissions in the * 328 * ILAPR. * 329 * * 330 ************************************************************************/ 331 332 typedef union ii_ilapo_u { 333 u64 ii_ilapo_regval; 334 struct { 335 u64 i_io_ovrride:64; 336 } ii_ilapo_fld_s; 337 } ii_ilapo_u_t; 338 339 /************************************************************************ 340 * * 341 * This register qualifies all the PIO and Graphics writes launched * 342 * from the SHUB towards a widget. * 343 * * 344 ************************************************************************/ 345 346 typedef union ii_iowa_u { 347 u64 ii_iowa_regval; 348 struct { 349 u64 i_w0_oac:1; 350 u64 i_rsvd_1:7; 351 u64 i_wx_oac:8; 352 u64 i_rsvd:48; 353 } ii_iowa_fld_s; 354 } ii_iowa_u_t; 355 356 /************************************************************************ 357 * * 358 * Description: This register qualifies all the requests launched * 359 * from a widget towards the Shub. This register is intended to be * 360 * used by software in case of misbehaving widgets. * 361 * * 362 * * 363 ************************************************************************/ 364 365 typedef union ii_iiwa_u { 366 u64 ii_iiwa_regval; 367 struct { 368 u64 i_w0_iac:1; 369 u64 i_rsvd_1:7; 370 u64 i_wx_iac:8; 371 u64 i_rsvd:48; 372 } ii_iiwa_fld_s; 373 } ii_iiwa_u_t; 374 375 /************************************************************************ 376 * * 377 * Description: This register qualifies all the operations launched * 378 * from a widget towards the SHub. It allows individual access * 379 * control for up to 8 devices per widget. A device refers to * 380 * individual DMA master hosted by a widget. * 381 * The bits in each field of this register are cleared by the Shub * 382 * upon detection of an error which requires the device to be * 383 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric * 384 * Crosstalk). Whether or not a device has access rights to this * 385 * Shub is determined by an AND of the device enable bit in the * 386 * appropriate field of this register and the corresponding bit in * 387 * the Wx_IAC field (for the widget which this device belongs to). * 388 * The bits in this field are set by writing a 1 to them. Incoming * 389 * replies from Crosstalk are not subject to this access control * 390 * mechanism. * 391 * * 392 ************************************************************************/ 393 394 typedef union ii_iidem_u { 395 u64 ii_iidem_regval; 396 struct { 397 u64 i_w8_dxs:8; 398 u64 i_w9_dxs:8; 399 u64 i_wa_dxs:8; 400 u64 i_wb_dxs:8; 401 u64 i_wc_dxs:8; 402 u64 i_wd_dxs:8; 403 u64 i_we_dxs:8; 404 u64 i_wf_dxs:8; 405 } ii_iidem_fld_s; 406 } ii_iidem_u_t; 407 408 /************************************************************************ 409 * * 410 * This register contains the various programmable fields necessary * 411 * for controlling and observing the LLP signals. * 412 * * 413 ************************************************************************/ 414 415 typedef union ii_ilcsr_u { 416 u64 ii_ilcsr_regval; 417 struct { 418 u64 i_nullto:6; 419 u64 i_rsvd_4:2; 420 u64 i_wrmrst:1; 421 u64 i_rsvd_3:1; 422 u64 i_llp_en:1; 423 u64 i_bm8:1; 424 u64 i_llp_stat:2; 425 u64 i_remote_power:1; 426 u64 i_rsvd_2:1; 427 u64 i_maxrtry:10; 428 u64 i_d_avail_sel:2; 429 u64 i_rsvd_1:4; 430 u64 i_maxbrst:10; 431 u64 i_rsvd:22; 432 433 } ii_ilcsr_fld_s; 434 } ii_ilcsr_u_t; 435 436 /************************************************************************ 437 * * 438 * This is simply a status registers that monitors the LLP error * 439 * rate. * 440 * * 441 ************************************************************************/ 442 443 typedef union ii_illr_u { 444 u64 ii_illr_regval; 445 struct { 446 u64 i_sn_cnt:16; 447 u64 i_cb_cnt:16; 448 u64 i_rsvd:32; 449 } ii_illr_fld_s; 450 } ii_illr_u_t; 451 452 /************************************************************************ 453 * * 454 * Description: All II-detected non-BTE error interrupts are * 455 * specified via this register. * 456 * NOTE: The PI interrupt register address is hardcoded in the II. If * 457 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI * 458 * packet) to address offset 0x0180_0090 within the local register * 459 * address space of PI0 on the node specified by the NODE field. If * 460 * PI_ID==1, then the II sends the interrupt request to address * 461 * offset 0x01A0_0090 within the local register address space of PI1 * 462 * on the node specified by the NODE field. * 463 * * 464 ************************************************************************/ 465 466 typedef union ii_iidsr_u { 467 u64 ii_iidsr_regval; 468 struct { 469 u64 i_level:8; 470 u64 i_pi_id:1; 471 u64 i_node:11; 472 u64 i_rsvd_3:4; 473 u64 i_enable:1; 474 u64 i_rsvd_2:3; 475 u64 i_int_sent:2; 476 u64 i_rsvd_1:2; 477 u64 i_pi0_forward_int:1; 478 u64 i_pi1_forward_int:1; 479 u64 i_rsvd:30; 480 } ii_iidsr_fld_s; 481 } ii_iidsr_u_t; 482 483 /************************************************************************ 484 * * 485 * There are two instances of this register. This register is used * 486 * for matching up the incoming responses from the graphics widget to * 487 * the processor that initiated the graphics operation. The * 488 * write-responses are converted to graphics credits and returned to * 489 * the processor so that the processor interface can manage the flow * 490 * control. * 491 * * 492 ************************************************************************/ 493 494 typedef union ii_igfx0_u { 495 u64 ii_igfx0_regval; 496 struct { 497 u64 i_w_num:4; 498 u64 i_pi_id:1; 499 u64 i_n_num:12; 500 u64 i_p_num:1; 501 u64 i_rsvd:46; 502 } ii_igfx0_fld_s; 503 } ii_igfx0_u_t; 504 505 /************************************************************************ 506 * * 507 * There are two instances of this register. This register is used * 508 * for matching up the incoming responses from the graphics widget to * 509 * the processor that initiated the graphics operation. The * 510 * write-responses are converted to graphics credits and returned to * 511 * the processor so that the processor interface can manage the flow * 512 * control. * 513 * * 514 ************************************************************************/ 515 516 typedef union ii_igfx1_u { 517 u64 ii_igfx1_regval; 518 struct { 519 u64 i_w_num:4; 520 u64 i_pi_id:1; 521 u64 i_n_num:12; 522 u64 i_p_num:1; 523 u64 i_rsvd:46; 524 } ii_igfx1_fld_s; 525 } ii_igfx1_u_t; 526 527 /************************************************************************ 528 * * 529 * There are two instances of this registers. These registers are * 530 * used as scratch registers for software use. * 531 * * 532 ************************************************************************/ 533 534 typedef union ii_iscr0_u { 535 u64 ii_iscr0_regval; 536 struct { 537 u64 i_scratch:64; 538 } ii_iscr0_fld_s; 539 } ii_iscr0_u_t; 540 541 /************************************************************************ 542 * * 543 * There are two instances of this registers. These registers are * 544 * used as scratch registers for software use. * 545 * * 546 ************************************************************************/ 547 548 typedef union ii_iscr1_u { 549 u64 ii_iscr1_regval; 550 struct { 551 u64 i_scratch:64; 552 } ii_iscr1_fld_s; 553 } ii_iscr1_u_t; 554 555 /************************************************************************ 556 * * 557 * Description: There are seven instances of translation table entry * 558 * registers. Each register maps a Shub Big Window to a 48-bit * 559 * address on Crosstalk. * 560 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 561 * number) are used to select one of these 7 registers. The Widget * 562 * number field is then derived from the W_NUM field for synthesizing * 563 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 564 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 565 * are padded with zeros. Although the maximum Crosstalk space * 566 * addressable by the SHub is thus the lower 16 GBytes per widget * 567 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 568 * space can be accessed. * 569 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 570 * Window number) are used to select one of these 7 registers. The * 571 * Widget number field is then derived from the W_NUM field for * 572 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 573 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 574 * field is used as Crosstalk[47], and remainder of the Crosstalk * 575 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 576 * Crosstalk space addressable by the Shub is thus the lower * 577 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 578 * of this space can be accessed. * 579 * * 580 ************************************************************************/ 581 582 typedef union ii_itte1_u { 583 u64 ii_itte1_regval; 584 struct { 585 u64 i_offset:5; 586 u64 i_rsvd_1:3; 587 u64 i_w_num:4; 588 u64 i_iosp:1; 589 u64 i_rsvd:51; 590 } ii_itte1_fld_s; 591 } ii_itte1_u_t; 592 593 /************************************************************************ 594 * * 595 * Description: There are seven instances of translation table entry * 596 * registers. Each register maps a Shub Big Window to a 48-bit * 597 * address on Crosstalk. * 598 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 599 * number) are used to select one of these 7 registers. The Widget * 600 * number field is then derived from the W_NUM field for synthesizing * 601 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 602 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 603 * are padded with zeros. Although the maximum Crosstalk space * 604 * addressable by the Shub is thus the lower 16 GBytes per widget * 605 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 606 * space can be accessed. * 607 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 608 * Window number) are used to select one of these 7 registers. The * 609 * Widget number field is then derived from the W_NUM field for * 610 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 611 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 612 * field is used as Crosstalk[47], and remainder of the Crosstalk * 613 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 614 * Crosstalk space addressable by the Shub is thus the lower * 615 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 616 * of this space can be accessed. * 617 * * 618 ************************************************************************/ 619 620 typedef union ii_itte2_u { 621 u64 ii_itte2_regval; 622 struct { 623 u64 i_offset:5; 624 u64 i_rsvd_1:3; 625 u64 i_w_num:4; 626 u64 i_iosp:1; 627 u64 i_rsvd:51; 628 } ii_itte2_fld_s; 629 } ii_itte2_u_t; 630 631 /************************************************************************ 632 * * 633 * Description: There are seven instances of translation table entry * 634 * registers. Each register maps a Shub Big Window to a 48-bit * 635 * address on Crosstalk. * 636 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 637 * number) are used to select one of these 7 registers. The Widget * 638 * number field is then derived from the W_NUM field for synthesizing * 639 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 640 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 641 * are padded with zeros. Although the maximum Crosstalk space * 642 * addressable by the Shub is thus the lower 16 GBytes per widget * 643 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 644 * space can be accessed. * 645 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 646 * Window number) are used to select one of these 7 registers. The * 647 * Widget number field is then derived from the W_NUM field for * 648 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 649 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 650 * field is used as Crosstalk[47], and remainder of the Crosstalk * 651 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 652 * Crosstalk space addressable by the SHub is thus the lower * 653 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 654 * of this space can be accessed. * 655 * * 656 ************************************************************************/ 657 658 typedef union ii_itte3_u { 659 u64 ii_itte3_regval; 660 struct { 661 u64 i_offset:5; 662 u64 i_rsvd_1:3; 663 u64 i_w_num:4; 664 u64 i_iosp:1; 665 u64 i_rsvd:51; 666 } ii_itte3_fld_s; 667 } ii_itte3_u_t; 668 669 /************************************************************************ 670 * * 671 * Description: There are seven instances of translation table entry * 672 * registers. Each register maps a SHub Big Window to a 48-bit * 673 * address on Crosstalk. * 674 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 675 * number) are used to select one of these 7 registers. The Widget * 676 * number field is then derived from the W_NUM field for synthesizing * 677 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 678 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 679 * are padded with zeros. Although the maximum Crosstalk space * 680 * addressable by the SHub is thus the lower 16 GBytes per widget * 681 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 682 * space can be accessed. * 683 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 684 * Window number) are used to select one of these 7 registers. The * 685 * Widget number field is then derived from the W_NUM field for * 686 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 687 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 688 * field is used as Crosstalk[47], and remainder of the Crosstalk * 689 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 690 * Crosstalk space addressable by the SHub is thus the lower * 691 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 692 * of this space can be accessed. * 693 * * 694 ************************************************************************/ 695 696 typedef union ii_itte4_u { 697 u64 ii_itte4_regval; 698 struct { 699 u64 i_offset:5; 700 u64 i_rsvd_1:3; 701 u64 i_w_num:4; 702 u64 i_iosp:1; 703 u64 i_rsvd:51; 704 } ii_itte4_fld_s; 705 } ii_itte4_u_t; 706 707 /************************************************************************ 708 * * 709 * Description: There are seven instances of translation table entry * 710 * registers. Each register maps a SHub Big Window to a 48-bit * 711 * address on Crosstalk. * 712 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 713 * number) are used to select one of these 7 registers. The Widget * 714 * number field is then derived from the W_NUM field for synthesizing * 715 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 716 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 717 * are padded with zeros. Although the maximum Crosstalk space * 718 * addressable by the Shub is thus the lower 16 GBytes per widget * 719 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 720 * space can be accessed. * 721 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 722 * Window number) are used to select one of these 7 registers. The * 723 * Widget number field is then derived from the W_NUM field for * 724 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 725 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 726 * field is used as Crosstalk[47], and remainder of the Crosstalk * 727 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 728 * Crosstalk space addressable by the Shub is thus the lower * 729 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 730 * of this space can be accessed. * 731 * * 732 ************************************************************************/ 733 734 typedef union ii_itte5_u { 735 u64 ii_itte5_regval; 736 struct { 737 u64 i_offset:5; 738 u64 i_rsvd_1:3; 739 u64 i_w_num:4; 740 u64 i_iosp:1; 741 u64 i_rsvd:51; 742 } ii_itte5_fld_s; 743 } ii_itte5_u_t; 744 745 /************************************************************************ 746 * * 747 * Description: There are seven instances of translation table entry * 748 * registers. Each register maps a Shub Big Window to a 48-bit * 749 * address on Crosstalk. * 750 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 751 * number) are used to select one of these 7 registers. The Widget * 752 * number field is then derived from the W_NUM field for synthesizing * 753 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 754 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 755 * are padded with zeros. Although the maximum Crosstalk space * 756 * addressable by the Shub is thus the lower 16 GBytes per widget * 757 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 758 * space can be accessed. * 759 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 760 * Window number) are used to select one of these 7 registers. The * 761 * Widget number field is then derived from the W_NUM field for * 762 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 763 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 764 * field is used as Crosstalk[47], and remainder of the Crosstalk * 765 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 766 * Crosstalk space addressable by the Shub is thus the lower * 767 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 768 * of this space can be accessed. * 769 * * 770 ************************************************************************/ 771 772 typedef union ii_itte6_u { 773 u64 ii_itte6_regval; 774 struct { 775 u64 i_offset:5; 776 u64 i_rsvd_1:3; 777 u64 i_w_num:4; 778 u64 i_iosp:1; 779 u64 i_rsvd:51; 780 } ii_itte6_fld_s; 781 } ii_itte6_u_t; 782 783 /************************************************************************ 784 * * 785 * Description: There are seven instances of translation table entry * 786 * registers. Each register maps a Shub Big Window to a 48-bit * 787 * address on Crosstalk. * 788 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 789 * number) are used to select one of these 7 registers. The Widget * 790 * number field is then derived from the W_NUM field for synthesizing * 791 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 792 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 793 * are padded with zeros. Although the maximum Crosstalk space * 794 * addressable by the Shub is thus the lower 16 GBytes per widget * 795 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 796 * space can be accessed. * 797 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 798 * Window number) are used to select one of these 7 registers. The * 799 * Widget number field is then derived from the W_NUM field for * 800 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 801 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 802 * field is used as Crosstalk[47], and remainder of the Crosstalk * 803 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 804 * Crosstalk space addressable by the SHub is thus the lower * 805 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 806 * of this space can be accessed. * 807 * * 808 ************************************************************************/ 809 810 typedef union ii_itte7_u { 811 u64 ii_itte7_regval; 812 struct { 813 u64 i_offset:5; 814 u64 i_rsvd_1:3; 815 u64 i_w_num:4; 816 u64 i_iosp:1; 817 u64 i_rsvd:51; 818 } ii_itte7_fld_s; 819 } ii_itte7_u_t; 820 821 /************************************************************************ 822 * * 823 * Description: There are 9 instances of this register, one per * 824 * actual widget in this implementation of SHub and Crossbow. * 825 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 826 * refers to Crossbow's internal space. * 827 * This register contains the state elements per widget that are * 828 * necessary to manage the PIO flow control on Crosstalk and on the * 829 * Router Network. See the PIO Flow Control chapter for a complete * 830 * description of this register * 831 * The SPUR_WR bit requires some explanation. When this register is * 832 * written, the new value of the C field is captured in an internal * 833 * register so the hardware can remember what the programmer wrote * 834 * into the credit counter. The SPUR_WR bit sets whenever the C field * 835 * increments above this stored value, which indicates that there * 836 * have been more responses received than requests sent. The SPUR_WR * 837 * bit cannot be cleared until a value is written to the IPRBx * 838 * register; the write will correct the C field and capture its new * 839 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 840 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 841 * . * 842 * * 843 ************************************************************************/ 844 845 typedef union ii_iprb0_u { 846 u64 ii_iprb0_regval; 847 struct { 848 u64 i_c:8; 849 u64 i_na:14; 850 u64 i_rsvd_2:2; 851 u64 i_nb:14; 852 u64 i_rsvd_1:2; 853 u64 i_m:2; 854 u64 i_f:1; 855 u64 i_of_cnt:5; 856 u64 i_error:1; 857 u64 i_rd_to:1; 858 u64 i_spur_wr:1; 859 u64 i_spur_rd:1; 860 u64 i_rsvd:11; 861 u64 i_mult_err:1; 862 } ii_iprb0_fld_s; 863 } ii_iprb0_u_t; 864 865 /************************************************************************ 866 * * 867 * Description: There are 9 instances of this register, one per * 868 * actual widget in this implementation of SHub and Crossbow. * 869 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 870 * refers to Crossbow's internal space. * 871 * This register contains the state elements per widget that are * 872 * necessary to manage the PIO flow control on Crosstalk and on the * 873 * Router Network. See the PIO Flow Control chapter for a complete * 874 * description of this register * 875 * The SPUR_WR bit requires some explanation. When this register is * 876 * written, the new value of the C field is captured in an internal * 877 * register so the hardware can remember what the programmer wrote * 878 * into the credit counter. The SPUR_WR bit sets whenever the C field * 879 * increments above this stored value, which indicates that there * 880 * have been more responses received than requests sent. The SPUR_WR * 881 * bit cannot be cleared until a value is written to the IPRBx * 882 * register; the write will correct the C field and capture its new * 883 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 884 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 885 * . * 886 * * 887 ************************************************************************/ 888 889 typedef union ii_iprb8_u { 890 u64 ii_iprb8_regval; 891 struct { 892 u64 i_c:8; 893 u64 i_na:14; 894 u64 i_rsvd_2:2; 895 u64 i_nb:14; 896 u64 i_rsvd_1:2; 897 u64 i_m:2; 898 u64 i_f:1; 899 u64 i_of_cnt:5; 900 u64 i_error:1; 901 u64 i_rd_to:1; 902 u64 i_spur_wr:1; 903 u64 i_spur_rd:1; 904 u64 i_rsvd:11; 905 u64 i_mult_err:1; 906 } ii_iprb8_fld_s; 907 } ii_iprb8_u_t; 908 909 /************************************************************************ 910 * * 911 * Description: There are 9 instances of this register, one per * 912 * actual widget in this implementation of SHub and Crossbow. * 913 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 914 * refers to Crossbow's internal space. * 915 * This register contains the state elements per widget that are * 916 * necessary to manage the PIO flow control on Crosstalk and on the * 917 * Router Network. See the PIO Flow Control chapter for a complete * 918 * description of this register * 919 * The SPUR_WR bit requires some explanation. When this register is * 920 * written, the new value of the C field is captured in an internal * 921 * register so the hardware can remember what the programmer wrote * 922 * into the credit counter. The SPUR_WR bit sets whenever the C field * 923 * increments above this stored value, which indicates that there * 924 * have been more responses received than requests sent. The SPUR_WR * 925 * bit cannot be cleared until a value is written to the IPRBx * 926 * register; the write will correct the C field and capture its new * 927 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 928 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 929 * . * 930 * * 931 ************************************************************************/ 932 933 typedef union ii_iprb9_u { 934 u64 ii_iprb9_regval; 935 struct { 936 u64 i_c:8; 937 u64 i_na:14; 938 u64 i_rsvd_2:2; 939 u64 i_nb:14; 940 u64 i_rsvd_1:2; 941 u64 i_m:2; 942 u64 i_f:1; 943 u64 i_of_cnt:5; 944 u64 i_error:1; 945 u64 i_rd_to:1; 946 u64 i_spur_wr:1; 947 u64 i_spur_rd:1; 948 u64 i_rsvd:11; 949 u64 i_mult_err:1; 950 } ii_iprb9_fld_s; 951 } ii_iprb9_u_t; 952 953 /************************************************************************ 954 * * 955 * Description: There are 9 instances of this register, one per * 956 * actual widget in this implementation of SHub and Crossbow. * 957 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 958 * refers to Crossbow's internal space. * 959 * This register contains the state elements per widget that are * 960 * necessary to manage the PIO flow control on Crosstalk and on the * 961 * Router Network. See the PIO Flow Control chapter for a complete * 962 * description of this register * 963 * The SPUR_WR bit requires some explanation. When this register is * 964 * written, the new value of the C field is captured in an internal * 965 * register so the hardware can remember what the programmer wrote * 966 * into the credit counter. The SPUR_WR bit sets whenever the C field * 967 * increments above this stored value, which indicates that there * 968 * have been more responses received than requests sent. The SPUR_WR * 969 * bit cannot be cleared until a value is written to the IPRBx * 970 * register; the write will correct the C field and capture its new * 971 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 972 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 973 * * 974 * * 975 ************************************************************************/ 976 977 typedef union ii_iprba_u { 978 u64 ii_iprba_regval; 979 struct { 980 u64 i_c:8; 981 u64 i_na:14; 982 u64 i_rsvd_2:2; 983 u64 i_nb:14; 984 u64 i_rsvd_1:2; 985 u64 i_m:2; 986 u64 i_f:1; 987 u64 i_of_cnt:5; 988 u64 i_error:1; 989 u64 i_rd_to:1; 990 u64 i_spur_wr:1; 991 u64 i_spur_rd:1; 992 u64 i_rsvd:11; 993 u64 i_mult_err:1; 994 } ii_iprba_fld_s; 995 } ii_iprba_u_t; 996 997 /************************************************************************ 998 * * 999 * Description: There are 9 instances of this register, one per * 1000 * actual widget in this implementation of SHub and Crossbow. * 1001 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1002 * refers to Crossbow's internal space. * 1003 * This register contains the state elements per widget that are * 1004 * necessary to manage the PIO flow control on Crosstalk and on the * 1005 * Router Network. See the PIO Flow Control chapter for a complete * 1006 * description of this register * 1007 * The SPUR_WR bit requires some explanation. When this register is * 1008 * written, the new value of the C field is captured in an internal * 1009 * register so the hardware can remember what the programmer wrote * 1010 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1011 * increments above this stored value, which indicates that there * 1012 * have been more responses received than requests sent. The SPUR_WR * 1013 * bit cannot be cleared until a value is written to the IPRBx * 1014 * register; the write will correct the C field and capture its new * 1015 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1016 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1017 * . * 1018 * * 1019 ************************************************************************/ 1020 1021 typedef union ii_iprbb_u { 1022 u64 ii_iprbb_regval; 1023 struct { 1024 u64 i_c:8; 1025 u64 i_na:14; 1026 u64 i_rsvd_2:2; 1027 u64 i_nb:14; 1028 u64 i_rsvd_1:2; 1029 u64 i_m:2; 1030 u64 i_f:1; 1031 u64 i_of_cnt:5; 1032 u64 i_error:1; 1033 u64 i_rd_to:1; 1034 u64 i_spur_wr:1; 1035 u64 i_spur_rd:1; 1036 u64 i_rsvd:11; 1037 u64 i_mult_err:1; 1038 } ii_iprbb_fld_s; 1039 } ii_iprbb_u_t; 1040 1041 /************************************************************************ 1042 * * 1043 * Description: There are 9 instances of this register, one per * 1044 * actual widget in this implementation of SHub and Crossbow. * 1045 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1046 * refers to Crossbow's internal space. * 1047 * This register contains the state elements per widget that are * 1048 * necessary to manage the PIO flow control on Crosstalk and on the * 1049 * Router Network. See the PIO Flow Control chapter for a complete * 1050 * description of this register * 1051 * The SPUR_WR bit requires some explanation. When this register is * 1052 * written, the new value of the C field is captured in an internal * 1053 * register so the hardware can remember what the programmer wrote * 1054 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1055 * increments above this stored value, which indicates that there * 1056 * have been more responses received than requests sent. The SPUR_WR * 1057 * bit cannot be cleared until a value is written to the IPRBx * 1058 * register; the write will correct the C field and capture its new * 1059 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1060 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1061 * . * 1062 * * 1063 ************************************************************************/ 1064 1065 typedef union ii_iprbc_u { 1066 u64 ii_iprbc_regval; 1067 struct { 1068 u64 i_c:8; 1069 u64 i_na:14; 1070 u64 i_rsvd_2:2; 1071 u64 i_nb:14; 1072 u64 i_rsvd_1:2; 1073 u64 i_m:2; 1074 u64 i_f:1; 1075 u64 i_of_cnt:5; 1076 u64 i_error:1; 1077 u64 i_rd_to:1; 1078 u64 i_spur_wr:1; 1079 u64 i_spur_rd:1; 1080 u64 i_rsvd:11; 1081 u64 i_mult_err:1; 1082 } ii_iprbc_fld_s; 1083 } ii_iprbc_u_t; 1084 1085 /************************************************************************ 1086 * * 1087 * Description: There are 9 instances of this register, one per * 1088 * actual widget in this implementation of SHub and Crossbow. * 1089 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1090 * refers to Crossbow's internal space. * 1091 * This register contains the state elements per widget that are * 1092 * necessary to manage the PIO flow control on Crosstalk and on the * 1093 * Router Network. See the PIO Flow Control chapter for a complete * 1094 * description of this register * 1095 * The SPUR_WR bit requires some explanation. When this register is * 1096 * written, the new value of the C field is captured in an internal * 1097 * register so the hardware can remember what the programmer wrote * 1098 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1099 * increments above this stored value, which indicates that there * 1100 * have been more responses received than requests sent. The SPUR_WR * 1101 * bit cannot be cleared until a value is written to the IPRBx * 1102 * register; the write will correct the C field and capture its new * 1103 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1104 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1105 * . * 1106 * * 1107 ************************************************************************/ 1108 1109 typedef union ii_iprbd_u { 1110 u64 ii_iprbd_regval; 1111 struct { 1112 u64 i_c:8; 1113 u64 i_na:14; 1114 u64 i_rsvd_2:2; 1115 u64 i_nb:14; 1116 u64 i_rsvd_1:2; 1117 u64 i_m:2; 1118 u64 i_f:1; 1119 u64 i_of_cnt:5; 1120 u64 i_error:1; 1121 u64 i_rd_to:1; 1122 u64 i_spur_wr:1; 1123 u64 i_spur_rd:1; 1124 u64 i_rsvd:11; 1125 u64 i_mult_err:1; 1126 } ii_iprbd_fld_s; 1127 } ii_iprbd_u_t; 1128 1129 /************************************************************************ 1130 * * 1131 * Description: There are 9 instances of this register, one per * 1132 * actual widget in this implementation of SHub and Crossbow. * 1133 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1134 * refers to Crossbow's internal space. * 1135 * This register contains the state elements per widget that are * 1136 * necessary to manage the PIO flow control on Crosstalk and on the * 1137 * Router Network. See the PIO Flow Control chapter for a complete * 1138 * description of this register * 1139 * The SPUR_WR bit requires some explanation. When this register is * 1140 * written, the new value of the C field is captured in an internal * 1141 * register so the hardware can remember what the programmer wrote * 1142 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1143 * increments above this stored value, which indicates that there * 1144 * have been more responses received than requests sent. The SPUR_WR * 1145 * bit cannot be cleared until a value is written to the IPRBx * 1146 * register; the write will correct the C field and capture its new * 1147 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1148 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1149 * . * 1150 * * 1151 ************************************************************************/ 1152 1153 typedef union ii_iprbe_u { 1154 u64 ii_iprbe_regval; 1155 struct { 1156 u64 i_c:8; 1157 u64 i_na:14; 1158 u64 i_rsvd_2:2; 1159 u64 i_nb:14; 1160 u64 i_rsvd_1:2; 1161 u64 i_m:2; 1162 u64 i_f:1; 1163 u64 i_of_cnt:5; 1164 u64 i_error:1; 1165 u64 i_rd_to:1; 1166 u64 i_spur_wr:1; 1167 u64 i_spur_rd:1; 1168 u64 i_rsvd:11; 1169 u64 i_mult_err:1; 1170 } ii_iprbe_fld_s; 1171 } ii_iprbe_u_t; 1172 1173 /************************************************************************ 1174 * * 1175 * Description: There are 9 instances of this register, one per * 1176 * actual widget in this implementation of Shub and Crossbow. * 1177 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1178 * refers to Crossbow's internal space. * 1179 * This register contains the state elements per widget that are * 1180 * necessary to manage the PIO flow control on Crosstalk and on the * 1181 * Router Network. See the PIO Flow Control chapter for a complete * 1182 * description of this register * 1183 * The SPUR_WR bit requires some explanation. When this register is * 1184 * written, the new value of the C field is captured in an internal * 1185 * register so the hardware can remember what the programmer wrote * 1186 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1187 * increments above this stored value, which indicates that there * 1188 * have been more responses received than requests sent. The SPUR_WR * 1189 * bit cannot be cleared until a value is written to the IPRBx * 1190 * register; the write will correct the C field and capture its new * 1191 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1192 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1193 * . * 1194 * * 1195 ************************************************************************/ 1196 1197 typedef union ii_iprbf_u { 1198 u64 ii_iprbf_regval; 1199 struct { 1200 u64 i_c:8; 1201 u64 i_na:14; 1202 u64 i_rsvd_2:2; 1203 u64 i_nb:14; 1204 u64 i_rsvd_1:2; 1205 u64 i_m:2; 1206 u64 i_f:1; 1207 u64 i_of_cnt:5; 1208 u64 i_error:1; 1209 u64 i_rd_to:1; 1210 u64 i_spur_wr:1; 1211 u64 i_spur_rd:1; 1212 u64 i_rsvd:11; 1213 u64 i_mult_err:1; 1214 } ii_iprbe_fld_s; 1215 } ii_iprbf_u_t; 1216 1217 /************************************************************************ 1218 * * 1219 * This register specifies the timeout value to use for monitoring * 1220 * Crosstalk credits which are used outbound to Crosstalk. An * 1221 * internal counter called the Crosstalk Credit Timeout Counter * 1222 * increments every 128 II clocks. The counter starts counting * 1223 * anytime the credit count drops below a threshold, and resets to * 1224 * zero (stops counting) anytime the credit count is at or above the * 1225 * threshold. The threshold is 1 credit in direct connect mode and 2 * 1226 * in Crossbow connect mode. When the internal Crosstalk Credit * 1227 * Timeout Counter reaches the value programmed in this register, a * 1228 * Crosstalk Credit Timeout has occurred. The internal counter is not * 1229 * readable from software, and stops counting at its maximum value, * 1230 * so it cannot cause more than one interrupt. * 1231 * * 1232 ************************************************************************/ 1233 1234 typedef union ii_ixcc_u { 1235 u64 ii_ixcc_regval; 1236 struct { 1237 u64 i_time_out:26; 1238 u64 i_rsvd:38; 1239 } ii_ixcc_fld_s; 1240 } ii_ixcc_u_t; 1241 1242 /************************************************************************ 1243 * * 1244 * Description: This register qualifies all the PIO and DMA * 1245 * operations launched from widget 0 towards the SHub. In * 1246 * addition, it also qualifies accesses by the BTE streams. * 1247 * The bits in each field of this register are cleared by the SHub * 1248 * upon detection of an error which requires widget 0 or the BTE * 1249 * streams to be terminated. Whether or not widget x has access * 1250 * rights to this SHub is determined by an AND of the device * 1251 * enable bit in the appropriate field of this register and bit 0 in * 1252 * the Wx_IAC field. The bits in this field are set by writing a 1 to * 1253 * them. Incoming replies from Crosstalk are not subject to this * 1254 * access control mechanism. * 1255 * * 1256 ************************************************************************/ 1257 1258 typedef union ii_imem_u { 1259 u64 ii_imem_regval; 1260 struct { 1261 u64 i_w0_esd:1; 1262 u64 i_rsvd_3:3; 1263 u64 i_b0_esd:1; 1264 u64 i_rsvd_2:3; 1265 u64 i_b1_esd:1; 1266 u64 i_rsvd_1:3; 1267 u64 i_clr_precise:1; 1268 u64 i_rsvd:51; 1269 } ii_imem_fld_s; 1270 } ii_imem_u_t; 1271 1272 /************************************************************************ 1273 * * 1274 * Description: This register specifies the timeout value to use for * 1275 * monitoring Crosstalk tail flits coming into the Shub in the * 1276 * TAIL_TO field. An internal counter associated with this register * 1277 * is incremented every 128 II internal clocks (7 bits). The counter * 1278 * starts counting anytime a header micropacket is received and stops * 1279 * counting (and resets to zero) any time a micropacket with a Tail * 1280 * bit is received. Once the counter reaches the threshold value * 1281 * programmed in this register, it generates an interrupt to the * 1282 * processor that is programmed into the IIDSR. The counter saturates * 1283 * (does not roll over) at its maximum value, so it cannot cause * 1284 * another interrupt until after it is cleared. * 1285 * The register also contains the Read Response Timeout values. The * 1286 * Prescalar is 23 bits, and counts II clocks. An internal counter * 1287 * increments on every II clock and when it reaches the value in the * 1288 * Prescalar field, all IPRTE registers with their valid bits set * 1289 * have their Read Response timers bumped. Whenever any of them match * 1290 * the value in the RRSP_TO field, a Read Response Timeout has * 1291 * occurred, and error handling occurs as described in the Error * 1292 * Handling section of this document. * 1293 * * 1294 ************************************************************************/ 1295 1296 typedef union ii_ixtt_u { 1297 u64 ii_ixtt_regval; 1298 struct { 1299 u64 i_tail_to:26; 1300 u64 i_rsvd_1:6; 1301 u64 i_rrsp_ps:23; 1302 u64 i_rrsp_to:5; 1303 u64 i_rsvd:4; 1304 } ii_ixtt_fld_s; 1305 } ii_ixtt_u_t; 1306 1307 /************************************************************************ 1308 * * 1309 * Writing a 1 to the fields of this register clears the appropriate * 1310 * error bits in other areas of SHub. Note that when the * 1311 * E_PRB_x bits are used to clear error bits in PRB registers, * 1312 * SPUR_RD and SPUR_WR may persist, because they require additional * 1313 * action to clear them. See the IPRBx and IXSS Register * 1314 * specifications. * 1315 * * 1316 ************************************************************************/ 1317 1318 typedef union ii_ieclr_u { 1319 u64 ii_ieclr_regval; 1320 struct { 1321 u64 i_e_prb_0:1; 1322 u64 i_rsvd:7; 1323 u64 i_e_prb_8:1; 1324 u64 i_e_prb_9:1; 1325 u64 i_e_prb_a:1; 1326 u64 i_e_prb_b:1; 1327 u64 i_e_prb_c:1; 1328 u64 i_e_prb_d:1; 1329 u64 i_e_prb_e:1; 1330 u64 i_e_prb_f:1; 1331 u64 i_e_crazy:1; 1332 u64 i_e_bte_0:1; 1333 u64 i_e_bte_1:1; 1334 u64 i_reserved_1:10; 1335 u64 i_spur_rd_hdr:1; 1336 u64 i_cam_intr_to:1; 1337 u64 i_cam_overflow:1; 1338 u64 i_cam_read_miss:1; 1339 u64 i_ioq_rep_underflow:1; 1340 u64 i_ioq_req_underflow:1; 1341 u64 i_ioq_rep_overflow:1; 1342 u64 i_ioq_req_overflow:1; 1343 u64 i_iiq_rep_overflow:1; 1344 u64 i_iiq_req_overflow:1; 1345 u64 i_ii_xn_rep_cred_overflow:1; 1346 u64 i_ii_xn_req_cred_overflow:1; 1347 u64 i_ii_xn_invalid_cmd:1; 1348 u64 i_xn_ii_invalid_cmd:1; 1349 u64 i_reserved_2:21; 1350 } ii_ieclr_fld_s; 1351 } ii_ieclr_u_t; 1352 1353 /************************************************************************ 1354 * * 1355 * This register controls both BTEs. SOFT_RESET is intended for * 1356 * recovery after an error. COUNT controls the total number of CRBs * 1357 * that both BTEs (combined) can use, which affects total BTE * 1358 * bandwidth. * 1359 * * 1360 ************************************************************************/ 1361 1362 typedef union ii_ibcr_u { 1363 u64 ii_ibcr_regval; 1364 struct { 1365 u64 i_count:4; 1366 u64 i_rsvd_1:4; 1367 u64 i_soft_reset:1; 1368 u64 i_rsvd:55; 1369 } ii_ibcr_fld_s; 1370 } ii_ibcr_u_t; 1371 1372 /************************************************************************ 1373 * * 1374 * This register contains the header of a spurious read response * 1375 * received from Crosstalk. A spurious read response is defined as a * 1376 * read response received by II from a widget for which (1) the SIDN * 1377 * has a value between 1 and 7, inclusive (II never sends requests to * 1378 * these widgets (2) there is no valid IPRTE register which * 1379 * corresponds to the TNUM, or (3) the widget indicated in SIDN is * 1380 * not the same as the widget recorded in the IPRTE register * 1381 * referenced by the TNUM. If this condition is true, and if the * 1382 * IXSS[VALID] bit is clear, then the header of the spurious read * 1383 * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The * 1384 * errant header is thereby captured, and no further spurious read * 1385 * respones are captured until IXSS[VALID] is cleared by setting the * 1386 * appropriate bit in IECLR. Every time a spurious read response is * 1387 * detected, the SPUR_RD bit of the PRB corresponding to the incoming * 1388 * message's SIDN field is set. This always happens, regarless of * 1389 * whether a header is captured. The programmer should check * 1390 * IXSM[SIDN] to determine which widget sent the spurious response, * 1391 * because there may be more than one SPUR_RD bit set in the PRB * 1392 * registers. The widget indicated by IXSM[SIDN] was the first * 1393 * spurious read response to be received since the last time * 1394 * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB * 1395 * will be set. Any SPUR_RD bits in any other PRB registers indicate * 1396 * spurious messages from other widets which were detected after the * 1397 * header was captured.. * 1398 * * 1399 ************************************************************************/ 1400 1401 typedef union ii_ixsm_u { 1402 u64 ii_ixsm_regval; 1403 struct { 1404 u64 i_byte_en:32; 1405 u64 i_reserved:1; 1406 u64 i_tag:3; 1407 u64 i_alt_pactyp:4; 1408 u64 i_bo:1; 1409 u64 i_error:1; 1410 u64 i_vbpm:1; 1411 u64 i_gbr:1; 1412 u64 i_ds:2; 1413 u64 i_ct:1; 1414 u64 i_tnum:5; 1415 u64 i_pactyp:4; 1416 u64 i_sidn:4; 1417 u64 i_didn:4; 1418 } ii_ixsm_fld_s; 1419 } ii_ixsm_u_t; 1420 1421 /************************************************************************ 1422 * * 1423 * This register contains the sideband bits of a spurious read * 1424 * response received from Crosstalk. * 1425 * * 1426 ************************************************************************/ 1427 1428 typedef union ii_ixss_u { 1429 u64 ii_ixss_regval; 1430 struct { 1431 u64 i_sideband:8; 1432 u64 i_rsvd:55; 1433 u64 i_valid:1; 1434 } ii_ixss_fld_s; 1435 } ii_ixss_u_t; 1436 1437 /************************************************************************ 1438 * * 1439 * This register enables software to access the II LLP's test port. * 1440 * Refer to the LLP 2.5 documentation for an explanation of the test * 1441 * port. Software can write to this register to program the values * 1442 * for the control fields (TestErrCapture, TestClear, TestFlit, * 1443 * TestMask and TestSeed). Similarly, software can read from this * 1444 * register to obtain the values of the test port's status outputs * 1445 * (TestCBerr, TestValid and TestData). * 1446 * * 1447 ************************************************************************/ 1448 1449 typedef union ii_ilct_u { 1450 u64 ii_ilct_regval; 1451 struct { 1452 u64 i_test_seed:20; 1453 u64 i_test_mask:8; 1454 u64 i_test_data:20; 1455 u64 i_test_valid:1; 1456 u64 i_test_cberr:1; 1457 u64 i_test_flit:3; 1458 u64 i_test_clear:1; 1459 u64 i_test_err_capture:1; 1460 u64 i_rsvd:9; 1461 } ii_ilct_fld_s; 1462 } ii_ilct_u_t; 1463 1464 /************************************************************************ 1465 * * 1466 * If the II detects an illegal incoming Duplonet packet (request or * 1467 * reply) when VALID==0 in the IIEPH1 register, then it saves the * 1468 * contents of the packet's header flit in the IIEPH1 and IIEPH2 * 1469 * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, * 1470 * and assigns a value to the ERR_TYPE field which indicates the * 1471 * specific nature of the error. The II recognizes four different * 1472 * types of errors: short request packets (ERR_TYPE==2), short reply * 1473 * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long * 1474 * reply packets (ERR_TYPE==5). The encodings for these types of * 1475 * errors were chosen to be consistent with the same types of errors * 1476 * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in * 1477 * the LB unit). If the II detects an illegal incoming Duplonet * 1478 * packet when VALID==1 in the IIEPH1 register, then it merely sets * 1479 * the OVERRUN bit to indicate that a subsequent error has happened, * 1480 * and does nothing further. * 1481 * * 1482 ************************************************************************/ 1483 1484 typedef union ii_iieph1_u { 1485 u64 ii_iieph1_regval; 1486 struct { 1487 u64 i_command:7; 1488 u64 i_rsvd_5:1; 1489 u64 i_suppl:14; 1490 u64 i_rsvd_4:1; 1491 u64 i_source:14; 1492 u64 i_rsvd_3:1; 1493 u64 i_err_type:4; 1494 u64 i_rsvd_2:4; 1495 u64 i_overrun:1; 1496 u64 i_rsvd_1:3; 1497 u64 i_valid:1; 1498 u64 i_rsvd:13; 1499 } ii_iieph1_fld_s; 1500 } ii_iieph1_u_t; 1501 1502 /************************************************************************ 1503 * * 1504 * This register holds the Address field from the header flit of an * 1505 * incoming erroneous Duplonet packet, along with the tail bit which * 1506 * accompanied this header flit. This register is essentially an * 1507 * extension of IIEPH1. Two registers were necessary because the 64 * 1508 * bits available in only a single register were insufficient to * 1509 * capture the entire header flit of an erroneous packet. * 1510 * * 1511 ************************************************************************/ 1512 1513 typedef union ii_iieph2_u { 1514 u64 ii_iieph2_regval; 1515 struct { 1516 u64 i_rsvd_0:3; 1517 u64 i_address:47; 1518 u64 i_rsvd_1:10; 1519 u64 i_tail:1; 1520 u64 i_rsvd:3; 1521 } ii_iieph2_fld_s; 1522 } ii_iieph2_u_t; 1523 1524 /******************************/ 1525 1526 /************************************************************************ 1527 * * 1528 * This register's value is a bit vector that guards access from SXBs * 1529 * to local registers within the II as well as to external Crosstalk * 1530 * widgets * 1531 * * 1532 ************************************************************************/ 1533 1534 typedef union ii_islapr_u { 1535 u64 ii_islapr_regval; 1536 struct { 1537 u64 i_region:64; 1538 } ii_islapr_fld_s; 1539 } ii_islapr_u_t; 1540 1541 /************************************************************************ 1542 * * 1543 * A write to this register of the 56-bit value "Pup+Bun" will cause * 1544 * the bit in the ISLAPR register corresponding to the region of the * 1545 * requestor to be set (access allowed). ( 1546 * * 1547 ************************************************************************/ 1548 1549 typedef union ii_islapo_u { 1550 u64 ii_islapo_regval; 1551 struct { 1552 u64 i_io_sbx_ovrride:56; 1553 u64 i_rsvd:8; 1554 } ii_islapo_fld_s; 1555 } ii_islapo_u_t; 1556 1557 /************************************************************************ 1558 * * 1559 * Determines how long the wrapper will wait aftr an interrupt is * 1560 * initially issued from the II before it times out the outstanding * 1561 * interrupt and drops it from the interrupt queue. * 1562 * * 1563 ************************************************************************/ 1564 1565 typedef union ii_iwi_u { 1566 u64 ii_iwi_regval; 1567 struct { 1568 u64 i_prescale:24; 1569 u64 i_rsvd:8; 1570 u64 i_timeout:8; 1571 u64 i_rsvd1:8; 1572 u64 i_intrpt_retry_period:8; 1573 u64 i_rsvd2:8; 1574 } ii_iwi_fld_s; 1575 } ii_iwi_u_t; 1576 1577 /************************************************************************ 1578 * * 1579 * Log errors which have occurred in the II wrapper. The errors are * 1580 * cleared by writing to the IECLR register. * 1581 * * 1582 ************************************************************************/ 1583 1584 typedef union ii_iwel_u { 1585 u64 ii_iwel_regval; 1586 struct { 1587 u64 i_intr_timed_out:1; 1588 u64 i_rsvd:7; 1589 u64 i_cam_overflow:1; 1590 u64 i_cam_read_miss:1; 1591 u64 i_rsvd1:2; 1592 u64 i_ioq_rep_underflow:1; 1593 u64 i_ioq_req_underflow:1; 1594 u64 i_ioq_rep_overflow:1; 1595 u64 i_ioq_req_overflow:1; 1596 u64 i_iiq_rep_overflow:1; 1597 u64 i_iiq_req_overflow:1; 1598 u64 i_rsvd2:6; 1599 u64 i_ii_xn_rep_cred_over_under:1; 1600 u64 i_ii_xn_req_cred_over_under:1; 1601 u64 i_rsvd3:6; 1602 u64 i_ii_xn_invalid_cmd:1; 1603 u64 i_xn_ii_invalid_cmd:1; 1604 u64 i_rsvd4:30; 1605 } ii_iwel_fld_s; 1606 } ii_iwel_u_t; 1607 1608 /************************************************************************ 1609 * * 1610 * Controls the II wrapper. * 1611 * * 1612 ************************************************************************/ 1613 1614 typedef union ii_iwc_u { 1615 u64 ii_iwc_regval; 1616 struct { 1617 u64 i_dma_byte_swap:1; 1618 u64 i_rsvd:3; 1619 u64 i_cam_read_lines_reset:1; 1620 u64 i_rsvd1:3; 1621 u64 i_ii_xn_cred_over_under_log:1; 1622 u64 i_rsvd2:19; 1623 u64 i_xn_rep_iq_depth:5; 1624 u64 i_rsvd3:3; 1625 u64 i_xn_req_iq_depth:5; 1626 u64 i_rsvd4:3; 1627 u64 i_iiq_depth:6; 1628 u64 i_rsvd5:12; 1629 u64 i_force_rep_cred:1; 1630 u64 i_force_req_cred:1; 1631 } ii_iwc_fld_s; 1632 } ii_iwc_u_t; 1633 1634 /************************************************************************ 1635 * * 1636 * Status in the II wrapper. * 1637 * * 1638 ************************************************************************/ 1639 1640 typedef union ii_iws_u { 1641 u64 ii_iws_regval; 1642 struct { 1643 u64 i_xn_rep_iq_credits:5; 1644 u64 i_rsvd:3; 1645 u64 i_xn_req_iq_credits:5; 1646 u64 i_rsvd1:51; 1647 } ii_iws_fld_s; 1648 } ii_iws_u_t; 1649 1650 /************************************************************************ 1651 * * 1652 * Masks errors in the IWEL register. * 1653 * * 1654 ************************************************************************/ 1655 1656 typedef union ii_iweim_u { 1657 u64 ii_iweim_regval; 1658 struct { 1659 u64 i_intr_timed_out:1; 1660 u64 i_rsvd:7; 1661 u64 i_cam_overflow:1; 1662 u64 i_cam_read_miss:1; 1663 u64 i_rsvd1:2; 1664 u64 i_ioq_rep_underflow:1; 1665 u64 i_ioq_req_underflow:1; 1666 u64 i_ioq_rep_overflow:1; 1667 u64 i_ioq_req_overflow:1; 1668 u64 i_iiq_rep_overflow:1; 1669 u64 i_iiq_req_overflow:1; 1670 u64 i_rsvd2:6; 1671 u64 i_ii_xn_rep_cred_overflow:1; 1672 u64 i_ii_xn_req_cred_overflow:1; 1673 u64 i_rsvd3:6; 1674 u64 i_ii_xn_invalid_cmd:1; 1675 u64 i_xn_ii_invalid_cmd:1; 1676 u64 i_rsvd4:30; 1677 } ii_iweim_fld_s; 1678 } ii_iweim_u_t; 1679 1680 /************************************************************************ 1681 * * 1682 * A write to this register causes a particular field in the * 1683 * corresponding widget's PRB entry to be adjusted up or down by 1. * 1684 * This counter should be used when recovering from error and reset * 1685 * conditions. Note that software would be capable of causing * 1686 * inadvertent overflow or underflow of these counters. * 1687 * * 1688 ************************************************************************/ 1689 1690 typedef union ii_ipca_u { 1691 u64 ii_ipca_regval; 1692 struct { 1693 u64 i_wid:4; 1694 u64 i_adjust:1; 1695 u64 i_rsvd_1:3; 1696 u64 i_field:2; 1697 u64 i_rsvd:54; 1698 } ii_ipca_fld_s; 1699 } ii_ipca_u_t; 1700 1701 /************************************************************************ 1702 * * 1703 * There are 8 instances of this register. This register contains * 1704 * the information that the II has to remember once it has launched a * 1705 * PIO Read operation. The contents are used to form the correct * 1706 * Router Network packet and direct the Crosstalk reply to the * 1707 * appropriate processor. * 1708 * * 1709 ************************************************************************/ 1710 1711 typedef union ii_iprte0a_u { 1712 u64 ii_iprte0a_regval; 1713 struct { 1714 u64 i_rsvd_1:54; 1715 u64 i_widget:4; 1716 u64 i_to_cnt:5; 1717 u64 i_vld:1; 1718 } ii_iprte0a_fld_s; 1719 } ii_iprte0a_u_t; 1720 1721 /************************************************************************ 1722 * * 1723 * There are 8 instances of this register. This register contains * 1724 * the information that the II has to remember once it has launched a * 1725 * PIO Read operation. The contents are used to form the correct * 1726 * Router Network packet and direct the Crosstalk reply to the * 1727 * appropriate processor. * 1728 * * 1729 ************************************************************************/ 1730 1731 typedef union ii_iprte1a_u { 1732 u64 ii_iprte1a_regval; 1733 struct { 1734 u64 i_rsvd_1:54; 1735 u64 i_widget:4; 1736 u64 i_to_cnt:5; 1737 u64 i_vld:1; 1738 } ii_iprte1a_fld_s; 1739 } ii_iprte1a_u_t; 1740 1741 /************************************************************************ 1742 * * 1743 * There are 8 instances of this register. This register contains * 1744 * the information that the II has to remember once it has launched a * 1745 * PIO Read operation. The contents are used to form the correct * 1746 * Router Network packet and direct the Crosstalk reply to the * 1747 * appropriate processor. * 1748 * * 1749 ************************************************************************/ 1750 1751 typedef union ii_iprte2a_u { 1752 u64 ii_iprte2a_regval; 1753 struct { 1754 u64 i_rsvd_1:54; 1755 u64 i_widget:4; 1756 u64 i_to_cnt:5; 1757 u64 i_vld:1; 1758 } ii_iprte2a_fld_s; 1759 } ii_iprte2a_u_t; 1760 1761 /************************************************************************ 1762 * * 1763 * There are 8 instances of this register. This register contains * 1764 * the information that the II has to remember once it has launched a * 1765 * PIO Read operation. The contents are used to form the correct * 1766 * Router Network packet and direct the Crosstalk reply to the * 1767 * appropriate processor. * 1768 * * 1769 ************************************************************************/ 1770 1771 typedef union ii_iprte3a_u { 1772 u64 ii_iprte3a_regval; 1773 struct { 1774 u64 i_rsvd_1:54; 1775 u64 i_widget:4; 1776 u64 i_to_cnt:5; 1777 u64 i_vld:1; 1778 } ii_iprte3a_fld_s; 1779 } ii_iprte3a_u_t; 1780 1781 /************************************************************************ 1782 * * 1783 * There are 8 instances of this register. This register contains * 1784 * the information that the II has to remember once it has launched a * 1785 * PIO Read operation. The contents are used to form the correct * 1786 * Router Network packet and direct the Crosstalk reply to the * 1787 * appropriate processor. * 1788 * * 1789 ************************************************************************/ 1790 1791 typedef union ii_iprte4a_u { 1792 u64 ii_iprte4a_regval; 1793 struct { 1794 u64 i_rsvd_1:54; 1795 u64 i_widget:4; 1796 u64 i_to_cnt:5; 1797 u64 i_vld:1; 1798 } ii_iprte4a_fld_s; 1799 } ii_iprte4a_u_t; 1800 1801 /************************************************************************ 1802 * * 1803 * There are 8 instances of this register. This register contains * 1804 * the information that the II has to remember once it has launched a * 1805 * PIO Read operation. The contents are used to form the correct * 1806 * Router Network packet and direct the Crosstalk reply to the * 1807 * appropriate processor. * 1808 * * 1809 ************************************************************************/ 1810 1811 typedef union ii_iprte5a_u { 1812 u64 ii_iprte5a_regval; 1813 struct { 1814 u64 i_rsvd_1:54; 1815 u64 i_widget:4; 1816 u64 i_to_cnt:5; 1817 u64 i_vld:1; 1818 } ii_iprte5a_fld_s; 1819 } ii_iprte5a_u_t; 1820 1821 /************************************************************************ 1822 * * 1823 * There are 8 instances of this register. This register contains * 1824 * the information that the II has to remember once it has launched a * 1825 * PIO Read operation. The contents are used to form the correct * 1826 * Router Network packet and direct the Crosstalk reply to the * 1827 * appropriate processor. * 1828 * * 1829 ************************************************************************/ 1830 1831 typedef union ii_iprte6a_u { 1832 u64 ii_iprte6a_regval; 1833 struct { 1834 u64 i_rsvd_1:54; 1835 u64 i_widget:4; 1836 u64 i_to_cnt:5; 1837 u64 i_vld:1; 1838 } ii_iprte6a_fld_s; 1839 } ii_iprte6a_u_t; 1840 1841 /************************************************************************ 1842 * * 1843 * There are 8 instances of this register. This register contains * 1844 * the information that the II has to remember once it has launched a * 1845 * PIO Read operation. The contents are used to form the correct * 1846 * Router Network packet and direct the Crosstalk reply to the * 1847 * appropriate processor. * 1848 * * 1849 ************************************************************************/ 1850 1851 typedef union ii_iprte7a_u { 1852 u64 ii_iprte7a_regval; 1853 struct { 1854 u64 i_rsvd_1:54; 1855 u64 i_widget:4; 1856 u64 i_to_cnt:5; 1857 u64 i_vld:1; 1858 } ii_iprtea7_fld_s; 1859 } ii_iprte7a_u_t; 1860 1861 /************************************************************************ 1862 * * 1863 * There are 8 instances of this register. This register contains * 1864 * the information that the II has to remember once it has launched a * 1865 * PIO Read operation. The contents are used to form the correct * 1866 * Router Network packet and direct the Crosstalk reply to the * 1867 * appropriate processor. * 1868 * * 1869 ************************************************************************/ 1870 1871 typedef union ii_iprte0b_u { 1872 u64 ii_iprte0b_regval; 1873 struct { 1874 u64 i_rsvd_1:3; 1875 u64 i_address:47; 1876 u64 i_init:3; 1877 u64 i_source:11; 1878 } ii_iprte0b_fld_s; 1879 } ii_iprte0b_u_t; 1880 1881 /************************************************************************ 1882 * * 1883 * There are 8 instances of this register. This register contains * 1884 * the information that the II has to remember once it has launched a * 1885 * PIO Read operation. The contents are used to form the correct * 1886 * Router Network packet and direct the Crosstalk reply to the * 1887 * appropriate processor. * 1888 * * 1889 ************************************************************************/ 1890 1891 typedef union ii_iprte1b_u { 1892 u64 ii_iprte1b_regval; 1893 struct { 1894 u64 i_rsvd_1:3; 1895 u64 i_address:47; 1896 u64 i_init:3; 1897 u64 i_source:11; 1898 } ii_iprte1b_fld_s; 1899 } ii_iprte1b_u_t; 1900 1901 /************************************************************************ 1902 * * 1903 * There are 8 instances of this register. This register contains * 1904 * the information that the II has to remember once it has launched a * 1905 * PIO Read operation. The contents are used to form the correct * 1906 * Router Network packet and direct the Crosstalk reply to the * 1907 * appropriate processor. * 1908 * * 1909 ************************************************************************/ 1910 1911 typedef union ii_iprte2b_u { 1912 u64 ii_iprte2b_regval; 1913 struct { 1914 u64 i_rsvd_1:3; 1915 u64 i_address:47; 1916 u64 i_init:3; 1917 u64 i_source:11; 1918 } ii_iprte2b_fld_s; 1919 } ii_iprte2b_u_t; 1920 1921 /************************************************************************ 1922 * * 1923 * There are 8 instances of this register. This register contains * 1924 * the information that the II has to remember once it has launched a * 1925 * PIO Read operation. The contents are used to form the correct * 1926 * Router Network packet and direct the Crosstalk reply to the * 1927 * appropriate processor. * 1928 * * 1929 ************************************************************************/ 1930 1931 typedef union ii_iprte3b_u { 1932 u64 ii_iprte3b_regval; 1933 struct { 1934 u64 i_rsvd_1:3; 1935 u64 i_address:47; 1936 u64 i_init:3; 1937 u64 i_source:11; 1938 } ii_iprte3b_fld_s; 1939 } ii_iprte3b_u_t; 1940 1941 /************************************************************************ 1942 * * 1943 * There are 8 instances of this register. This register contains * 1944 * the information that the II has to remember once it has launched a * 1945 * PIO Read operation. The contents are used to form the correct * 1946 * Router Network packet and direct the Crosstalk reply to the * 1947 * appropriate processor. * 1948 * * 1949 ************************************************************************/ 1950 1951 typedef union ii_iprte4b_u { 1952 u64 ii_iprte4b_regval; 1953 struct { 1954 u64 i_rsvd_1:3; 1955 u64 i_address:47; 1956 u64 i_init:3; 1957 u64 i_source:11; 1958 } ii_iprte4b_fld_s; 1959 } ii_iprte4b_u_t; 1960 1961 /************************************************************************ 1962 * * 1963 * There are 8 instances of this register. This register contains * 1964 * the information that the II has to remember once it has launched a * 1965 * PIO Read operation. The contents are used to form the correct * 1966 * Router Network packet and direct the Crosstalk reply to the * 1967 * appropriate processor. * 1968 * * 1969 ************************************************************************/ 1970 1971 typedef union ii_iprte5b_u { 1972 u64 ii_iprte5b_regval; 1973 struct { 1974 u64 i_rsvd_1:3; 1975 u64 i_address:47; 1976 u64 i_init:3; 1977 u64 i_source:11; 1978 } ii_iprte5b_fld_s; 1979 } ii_iprte5b_u_t; 1980 1981 /************************************************************************ 1982 * * 1983 * There are 8 instances of this register. This register contains * 1984 * the information that the II has to remember once it has launched a * 1985 * PIO Read operation. The contents are used to form the correct * 1986 * Router Network packet and direct the Crosstalk reply to the * 1987 * appropriate processor. * 1988 * * 1989 ************************************************************************/ 1990 1991 typedef union ii_iprte6b_u { 1992 u64 ii_iprte6b_regval; 1993 struct { 1994 u64 i_rsvd_1:3; 1995 u64 i_address:47; 1996 u64 i_init:3; 1997 u64 i_source:11; 1998 1999 } ii_iprte6b_fld_s; 2000 } ii_iprte6b_u_t; 2001 2002 /************************************************************************ 2003 * * 2004 * There are 8 instances of this register. This register contains * 2005 * the information that the II has to remember once it has launched a * 2006 * PIO Read operation. The contents are used to form the correct * 2007 * Router Network packet and direct the Crosstalk reply to the * 2008 * appropriate processor. * 2009 * * 2010 ************************************************************************/ 2011 2012 typedef union ii_iprte7b_u { 2013 u64 ii_iprte7b_regval; 2014 struct { 2015 u64 i_rsvd_1:3; 2016 u64 i_address:47; 2017 u64 i_init:3; 2018 u64 i_source:11; 2019 } ii_iprte7b_fld_s; 2020 } ii_iprte7b_u_t; 2021 2022 /************************************************************************ 2023 * * 2024 * Description: SHub II contains a feature which did not exist in * 2025 * the Hub which automatically cleans up after a Read Response * 2026 * timeout, including deallocation of the IPRTE and recovery of IBuf * 2027 * space. The inclusion of this register in SHub is for backward * 2028 * compatibility * 2029 * A write to this register causes an entry from the table of * 2030 * outstanding PIO Read Requests to be freed and returned to the * 2031 * stack of free entries. This register is used in handling the * 2032 * timeout errors that result in a PIO Reply never returning from * 2033 * Crosstalk. * 2034 * Note that this register does not affect the contents of the IPRTE * 2035 * registers. The Valid bits in those registers have to be * 2036 * specifically turned off by software. * 2037 * * 2038 ************************************************************************/ 2039 2040 typedef union ii_ipdr_u { 2041 u64 ii_ipdr_regval; 2042 struct { 2043 u64 i_te:3; 2044 u64 i_rsvd_1:1; 2045 u64 i_pnd:1; 2046 u64 i_init_rpcnt:1; 2047 u64 i_rsvd:58; 2048 } ii_ipdr_fld_s; 2049 } ii_ipdr_u_t; 2050 2051 /************************************************************************ 2052 * * 2053 * A write to this register causes a CRB entry to be returned to the * 2054 * queue of free CRBs. The entry should have previously been cleared * 2055 * (mark bit) via backdoor access to the pertinent CRB entry. This * 2056 * register is used in the last step of handling the errors that are * 2057 * captured and marked in CRB entries. Briefly: 1) first error for * 2058 * DMA write from a particular device, and first error for a * 2059 * particular BTE stream, lead to a marked CRB entry, and processor * 2060 * interrupt, 2) software reads the error information captured in the * 2061 * CRB entry, and presumably takes some corrective action, 3) * 2062 * software clears the mark bit, and finally 4) software writes to * 2063 * the ICDR register to return the CRB entry to the list of free CRB * 2064 * entries. * 2065 * * 2066 ************************************************************************/ 2067 2068 typedef union ii_icdr_u { 2069 u64 ii_icdr_regval; 2070 struct { 2071 u64 i_crb_num:4; 2072 u64 i_pnd:1; 2073 u64 i_rsvd:59; 2074 } ii_icdr_fld_s; 2075 } ii_icdr_u_t; 2076 2077 /************************************************************************ 2078 * * 2079 * This register provides debug access to two FIFOs inside of II. * 2080 * Both IOQ_MAX* fields of this register contain the instantaneous * 2081 * depth (in units of the number of available entries) of the * 2082 * associated IOQ FIFO. A read of this register will return the * 2083 * number of free entries on each FIFO at the time of the read. So * 2084 * when a FIFO is idle, the associated field contains the maximum * 2085 * depth of the FIFO. This register is writable for debug reasons * 2086 * and is intended to be written with the maximum desired FIFO depth * 2087 * while the FIFO is idle. Software must assure that II is idle when * 2088 * this register is written. If there are any active entries in any * 2089 * of these FIFOs when this register is written, the results are * 2090 * undefined. * 2091 * * 2092 ************************************************************************/ 2093 2094 typedef union ii_ifdr_u { 2095 u64 ii_ifdr_regval; 2096 struct { 2097 u64 i_ioq_max_rq:7; 2098 u64 i_set_ioq_rq:1; 2099 u64 i_ioq_max_rp:7; 2100 u64 i_set_ioq_rp:1; 2101 u64 i_rsvd:48; 2102 } ii_ifdr_fld_s; 2103 } ii_ifdr_u_t; 2104 2105 /************************************************************************ 2106 * * 2107 * This register allows the II to become sluggish in removing * 2108 * messages from its inbound queue (IIQ). This will cause messages to * 2109 * back up in either virtual channel. Disabling the "molasses" mode * 2110 * subsequently allows the II to be tested under stress. In the * 2111 * sluggish ("Molasses") mode, the localized effects of congestion * 2112 * can be observed. * 2113 * * 2114 ************************************************************************/ 2115 2116 typedef union ii_iiap_u { 2117 u64 ii_iiap_regval; 2118 struct { 2119 u64 i_rq_mls:6; 2120 u64 i_rsvd_1:2; 2121 u64 i_rp_mls:6; 2122 u64 i_rsvd:50; 2123 } ii_iiap_fld_s; 2124 } ii_iiap_u_t; 2125 2126 /************************************************************************ 2127 * * 2128 * This register allows several parameters of CRB operation to be * 2129 * set. Note that writing to this register can have catastrophic side * 2130 * effects, if the CRB is not quiescent, i.e. if the CRB is * 2131 * processing protocol messages when the write occurs. * 2132 * * 2133 ************************************************************************/ 2134 2135 typedef union ii_icmr_u { 2136 u64 ii_icmr_regval; 2137 struct { 2138 u64 i_sp_msg:1; 2139 u64 i_rd_hdr:1; 2140 u64 i_rsvd_4:2; 2141 u64 i_c_cnt:4; 2142 u64 i_rsvd_3:4; 2143 u64 i_clr_rqpd:1; 2144 u64 i_clr_rppd:1; 2145 u64 i_rsvd_2:2; 2146 u64 i_fc_cnt:4; 2147 u64 i_crb_vld:15; 2148 u64 i_crb_mark:15; 2149 u64 i_rsvd_1:2; 2150 u64 i_precise:1; 2151 u64 i_rsvd:11; 2152 } ii_icmr_fld_s; 2153 } ii_icmr_u_t; 2154 2155 /************************************************************************ 2156 * * 2157 * This register allows control of the table portion of the CRB * 2158 * logic via software. Control operations from this register have * 2159 * priority over all incoming Crosstalk or BTE requests. * 2160 * * 2161 ************************************************************************/ 2162 2163 typedef union ii_iccr_u { 2164 u64 ii_iccr_regval; 2165 struct { 2166 u64 i_crb_num:4; 2167 u64 i_rsvd_1:4; 2168 u64 i_cmd:8; 2169 u64 i_pending:1; 2170 u64 i_rsvd:47; 2171 } ii_iccr_fld_s; 2172 } ii_iccr_u_t; 2173 2174 /************************************************************************ 2175 * * 2176 * This register allows the maximum timeout value to be programmed. * 2177 * * 2178 ************************************************************************/ 2179 2180 typedef union ii_icto_u { 2181 u64 ii_icto_regval; 2182 struct { 2183 u64 i_timeout:8; 2184 u64 i_rsvd:56; 2185 } ii_icto_fld_s; 2186 } ii_icto_u_t; 2187 2188 /************************************************************************ 2189 * * 2190 * This register allows the timeout prescalar to be programmed. An * 2191 * internal counter is associated with this register. When the * 2192 * internal counter reaches the value of the PRESCALE field, the * 2193 * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * 2194 * field). The internal counter resets to zero, and then continues * 2195 * counting. * 2196 * * 2197 ************************************************************************/ 2198 2199 typedef union ii_ictp_u { 2200 u64 ii_ictp_regval; 2201 struct { 2202 u64 i_prescale:24; 2203 u64 i_rsvd:40; 2204 } ii_ictp_fld_s; 2205 } ii_ictp_u_t; 2206 2207 /************************************************************************ 2208 * * 2209 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2210 * used for Crosstalk operations (both cacheline and partial * 2211 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2212 * registers (_A to _E) are required to read and write each entry. * 2213 * The CRB Entry registers can be conceptualized as rows and columns * 2214 * (illustrated in the table above). Each row contains the 4 * 2215 * registers required for a single CRB Entry. The first doubleword * 2216 * (column) for each entry is labeled A, and the second doubleword * 2217 * (higher address) is labeled B, the third doubleword is labeled C, * 2218 * the fourth doubleword is labeled D and the fifth doubleword is * 2219 * labeled E. All CRB entries have their addresses on a quarter * 2220 * cacheline aligned boundary. * 2221 * Upon reset, only the following fields are initialized: valid * 2222 * (VLD), priority count, timeout, timeout valid, and context valid. * 2223 * All other bits should be cleared by software before use (after * 2224 * recovering any potential error state from before the reset). * 2225 * The following four tables summarize the format for the four * 2226 * registers that are used for each ICRB# Entry. * 2227 * * 2228 ************************************************************************/ 2229 2230 typedef union ii_icrb0_a_u { 2231 u64 ii_icrb0_a_regval; 2232 struct { 2233 u64 ia_iow:1; 2234 u64 ia_vld:1; 2235 u64 ia_addr:47; 2236 u64 ia_tnum:5; 2237 u64 ia_sidn:4; 2238 u64 ia_rsvd:6; 2239 } ii_icrb0_a_fld_s; 2240 } ii_icrb0_a_u_t; 2241 2242 /************************************************************************ 2243 * * 2244 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2245 * used for Crosstalk operations (both cacheline and partial * 2246 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2247 * registers (_A to _E) are required to read and write each entry. * 2248 * * 2249 ************************************************************************/ 2250 2251 typedef union ii_icrb0_b_u { 2252 u64 ii_icrb0_b_regval; 2253 struct { 2254 u64 ib_xt_err:1; 2255 u64 ib_mark:1; 2256 u64 ib_ln_uce:1; 2257 u64 ib_errcode:3; 2258 u64 ib_error:1; 2259 u64 ib_stall__bte_1:1; 2260 u64 ib_stall__bte_0:1; 2261 u64 ib_stall__intr:1; 2262 u64 ib_stall_ib:1; 2263 u64 ib_intvn:1; 2264 u64 ib_wb:1; 2265 u64 ib_hold:1; 2266 u64 ib_ack:1; 2267 u64 ib_resp:1; 2268 u64 ib_ack_cnt:11; 2269 u64 ib_rsvd:7; 2270 u64 ib_exc:5; 2271 u64 ib_init:3; 2272 u64 ib_imsg:8; 2273 u64 ib_imsgtype:2; 2274 u64 ib_use_old:1; 2275 u64 ib_rsvd_1:11; 2276 } ii_icrb0_b_fld_s; 2277 } ii_icrb0_b_u_t; 2278 2279 /************************************************************************ 2280 * * 2281 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2282 * used for Crosstalk operations (both cacheline and partial * 2283 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2284 * registers (_A to _E) are required to read and write each entry. * 2285 * * 2286 ************************************************************************/ 2287 2288 typedef union ii_icrb0_c_u { 2289 u64 ii_icrb0_c_regval; 2290 struct { 2291 u64 ic_source:15; 2292 u64 ic_size:2; 2293 u64 ic_ct:1; 2294 u64 ic_bte_num:1; 2295 u64 ic_gbr:1; 2296 u64 ic_resprqd:1; 2297 u64 ic_bo:1; 2298 u64 ic_suppl:15; 2299 u64 ic_rsvd:27; 2300 } ii_icrb0_c_fld_s; 2301 } ii_icrb0_c_u_t; 2302 2303 /************************************************************************ 2304 * * 2305 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2306 * used for Crosstalk operations (both cacheline and partial * 2307 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2308 * registers (_A to _E) are required to read and write each entry. * 2309 * * 2310 ************************************************************************/ 2311 2312 typedef union ii_icrb0_d_u { 2313 u64 ii_icrb0_d_regval; 2314 struct { 2315 u64 id_pa_be:43; 2316 u64 id_bte_op:1; 2317 u64 id_pr_psc:4; 2318 u64 id_pr_cnt:4; 2319 u64 id_sleep:1; 2320 u64 id_rsvd:11; 2321 } ii_icrb0_d_fld_s; 2322 } ii_icrb0_d_u_t; 2323 2324 /************************************************************************ 2325 * * 2326 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2327 * used for Crosstalk operations (both cacheline and partial * 2328 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2329 * registers (_A to _E) are required to read and write each entry. * 2330 * * 2331 ************************************************************************/ 2332 2333 typedef union ii_icrb0_e_u { 2334 u64 ii_icrb0_e_regval; 2335 struct { 2336 u64 ie_timeout:8; 2337 u64 ie_context:15; 2338 u64 ie_rsvd:1; 2339 u64 ie_tvld:1; 2340 u64 ie_cvld:1; 2341 u64 ie_rsvd_0:38; 2342 } ii_icrb0_e_fld_s; 2343 } ii_icrb0_e_u_t; 2344 2345 /************************************************************************ 2346 * * 2347 * This register contains the lower 64 bits of the header of the * 2348 * spurious message captured by II. Valid when the SP_MSG bit in ICMR * 2349 * register is set. * 2350 * * 2351 ************************************************************************/ 2352 2353 typedef union ii_icsml_u { 2354 u64 ii_icsml_regval; 2355 struct { 2356 u64 i_tt_addr:47; 2357 u64 i_newsuppl_ex:14; 2358 u64 i_reserved:2; 2359 u64 i_overflow:1; 2360 } ii_icsml_fld_s; 2361 } ii_icsml_u_t; 2362 2363 /************************************************************************ 2364 * * 2365 * This register contains the middle 64 bits of the header of the * 2366 * spurious message captured by II. Valid when the SP_MSG bit in ICMR * 2367 * register is set. * 2368 * * 2369 ************************************************************************/ 2370 2371 typedef union ii_icsmm_u { 2372 u64 ii_icsmm_regval; 2373 struct { 2374 u64 i_tt_ack_cnt:11; 2375 u64 i_reserved:53; 2376 } ii_icsmm_fld_s; 2377 } ii_icsmm_u_t; 2378 2379 /************************************************************************ 2380 * * 2381 * This register contains the microscopic state, all the inputs to * 2382 * the protocol table, captured with the spurious message. Valid when * 2383 * the SP_MSG bit in the ICMR register is set. * 2384 * * 2385 ************************************************************************/ 2386 2387 typedef union ii_icsmh_u { 2388 u64 ii_icsmh_regval; 2389 struct { 2390 u64 i_tt_vld:1; 2391 u64 i_xerr:1; 2392 u64 i_ft_cwact_o:1; 2393 u64 i_ft_wact_o:1; 2394 u64 i_ft_active_o:1; 2395 u64 i_sync:1; 2396 u64 i_mnusg:1; 2397 u64 i_mnusz:1; 2398 u64 i_plusz:1; 2399 u64 i_plusg:1; 2400 u64 i_tt_exc:5; 2401 u64 i_tt_wb:1; 2402 u64 i_tt_hold:1; 2403 u64 i_tt_ack:1; 2404 u64 i_tt_resp:1; 2405 u64 i_tt_intvn:1; 2406 u64 i_g_stall_bte1:1; 2407 u64 i_g_stall_bte0:1; 2408 u64 i_g_stall_il:1; 2409 u64 i_g_stall_ib:1; 2410 u64 i_tt_imsg:8; 2411 u64 i_tt_imsgtype:2; 2412 u64 i_tt_use_old:1; 2413 u64 i_tt_respreqd:1; 2414 u64 i_tt_bte_num:1; 2415 u64 i_cbn:1; 2416 u64 i_match:1; 2417 u64 i_rpcnt_lt_34:1; 2418 u64 i_rpcnt_ge_34:1; 2419 u64 i_rpcnt_lt_18:1; 2420 u64 i_rpcnt_ge_18:1; 2421 u64 i_rpcnt_lt_2:1; 2422 u64 i_rpcnt_ge_2:1; 2423 u64 i_rqcnt_lt_18:1; 2424 u64 i_rqcnt_ge_18:1; 2425 u64 i_rqcnt_lt_2:1; 2426 u64 i_rqcnt_ge_2:1; 2427 u64 i_tt_device:7; 2428 u64 i_tt_init:3; 2429 u64 i_reserved:5; 2430 } ii_icsmh_fld_s; 2431 } ii_icsmh_u_t; 2432 2433 /************************************************************************ 2434 * * 2435 * The Shub DEBUG unit provides a 3-bit selection signal to the * 2436 * II core and a 3-bit selection signal to the fsbclk domain in the II * 2437 * wrapper. * 2438 * * 2439 ************************************************************************/ 2440 2441 typedef union ii_idbss_u { 2442 u64 ii_idbss_regval; 2443 struct { 2444 u64 i_iioclk_core_submenu:3; 2445 u64 i_rsvd:5; 2446 u64 i_fsbclk_wrapper_submenu:3; 2447 u64 i_rsvd_1:5; 2448 u64 i_iioclk_menu:5; 2449 u64 i_rsvd_2:43; 2450 } ii_idbss_fld_s; 2451 } ii_idbss_u_t; 2452 2453 /************************************************************************ 2454 * * 2455 * Description: This register is used to set up the length for a * 2456 * transfer and then to monitor the progress of that transfer. This * 2457 * register needs to be initialized before a transfer is started. A * 2458 * legitimate write to this register will set the Busy bit, clear the * 2459 * Error bit, and initialize the length to the value desired. * 2460 * While the transfer is in progress, hardware will decrement the * 2461 * length field with each successful block that is copied. Once the * 2462 * transfer completes, hardware will clear the Busy bit. The length * 2463 * field will also contain the number of cache lines left to be * 2464 * transferred. * 2465 * * 2466 ************************************************************************/ 2467 2468 typedef union ii_ibls0_u { 2469 u64 ii_ibls0_regval; 2470 struct { 2471 u64 i_length:16; 2472 u64 i_error:1; 2473 u64 i_rsvd_1:3; 2474 u64 i_busy:1; 2475 u64 i_rsvd:43; 2476 } ii_ibls0_fld_s; 2477 } ii_ibls0_u_t; 2478 2479 /************************************************************************ 2480 * * 2481 * This register should be loaded before a transfer is started. The * 2482 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 2483 * address as described in Section 1.3, Figure2 and Figure3. Since * 2484 * the bottom 7 bits of the address are always taken to be zero, BTE * 2485 * transfers are always cacheline-aligned. * 2486 * * 2487 ************************************************************************/ 2488 2489 typedef union ii_ibsa0_u { 2490 u64 ii_ibsa0_regval; 2491 struct { 2492 u64 i_rsvd_1:7; 2493 u64 i_addr:42; 2494 u64 i_rsvd:15; 2495 } ii_ibsa0_fld_s; 2496 } ii_ibsa0_u_t; 2497 2498 /************************************************************************ 2499 * * 2500 * This register should be loaded before a transfer is started. The * 2501 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 2502 * address as described in Section 1.3, Figure2 and Figure3. Since * 2503 * the bottom 7 bits of the address are always taken to be zero, BTE * 2504 * transfers are always cacheline-aligned. * 2505 * * 2506 ************************************************************************/ 2507 2508 typedef union ii_ibda0_u { 2509 u64 ii_ibda0_regval; 2510 struct { 2511 u64 i_rsvd_1:7; 2512 u64 i_addr:42; 2513 u64 i_rsvd:15; 2514 } ii_ibda0_fld_s; 2515 } ii_ibda0_u_t; 2516 2517 /************************************************************************ 2518 * * 2519 * Writing to this register sets up the attributes of the transfer * 2520 * and initiates the transfer operation. Reading this register has * 2521 * the side effect of terminating any transfer in progress. Note: * 2522 * stopping a transfer midstream could have an adverse impact on the * 2523 * other BTE. If a BTE stream has to be stopped (due to error * 2524 * handling for example), both BTE streams should be stopped and * 2525 * their transfers discarded. * 2526 * * 2527 ************************************************************************/ 2528 2529 typedef union ii_ibct0_u { 2530 u64 ii_ibct0_regval; 2531 struct { 2532 u64 i_zerofill:1; 2533 u64 i_rsvd_2:3; 2534 u64 i_notify:1; 2535 u64 i_rsvd_1:3; 2536 u64 i_poison:1; 2537 u64 i_rsvd:55; 2538 } ii_ibct0_fld_s; 2539 } ii_ibct0_u_t; 2540 2541 /************************************************************************ 2542 * * 2543 * This register contains the address to which the WINV is sent. * 2544 * This address has to be cache line aligned. * 2545 * * 2546 ************************************************************************/ 2547 2548 typedef union ii_ibna0_u { 2549 u64 ii_ibna0_regval; 2550 struct { 2551 u64 i_rsvd_1:7; 2552 u64 i_addr:42; 2553 u64 i_rsvd:15; 2554 } ii_ibna0_fld_s; 2555 } ii_ibna0_u_t; 2556 2557 /************************************************************************ 2558 * * 2559 * This register contains the programmable level as well as the node * 2560 * ID and PI unit of the processor to which the interrupt will be * 2561 * sent. * 2562 * * 2563 ************************************************************************/ 2564 2565 typedef union ii_ibia0_u { 2566 u64 ii_ibia0_regval; 2567 struct { 2568 u64 i_rsvd_2:1; 2569 u64 i_node_id:11; 2570 u64 i_rsvd_1:4; 2571 u64 i_level:7; 2572 u64 i_rsvd:41; 2573 } ii_ibia0_fld_s; 2574 } ii_ibia0_u_t; 2575 2576 /************************************************************************ 2577 * * 2578 * Description: This register is used to set up the length for a * 2579 * transfer and then to monitor the progress of that transfer. This * 2580 * register needs to be initialized before a transfer is started. A * 2581 * legitimate write to this register will set the Busy bit, clear the * 2582 * Error bit, and initialize the length to the value desired. * 2583 * While the transfer is in progress, hardware will decrement the * 2584 * length field with each successful block that is copied. Once the * 2585 * transfer completes, hardware will clear the Busy bit. The length * 2586 * field will also contain the number of cache lines left to be * 2587 * transferred. * 2588 * * 2589 ************************************************************************/ 2590 2591 typedef union ii_ibls1_u { 2592 u64 ii_ibls1_regval; 2593 struct { 2594 u64 i_length:16; 2595 u64 i_error:1; 2596 u64 i_rsvd_1:3; 2597 u64 i_busy:1; 2598 u64 i_rsvd:43; 2599 } ii_ibls1_fld_s; 2600 } ii_ibls1_u_t; 2601 2602 /************************************************************************ 2603 * * 2604 * This register should be loaded before a transfer is started. The * 2605 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 2606 * address as described in Section 1.3, Figure2 and Figure3. Since * 2607 * the bottom 7 bits of the address are always taken to be zero, BTE * 2608 * transfers are always cacheline-aligned. * 2609 * * 2610 ************************************************************************/ 2611 2612 typedef union ii_ibsa1_u { 2613 u64 ii_ibsa1_regval; 2614 struct { 2615 u64 i_rsvd_1:7; 2616 u64 i_addr:33; 2617 u64 i_rsvd:24; 2618 } ii_ibsa1_fld_s; 2619 } ii_ibsa1_u_t; 2620 2621 /************************************************************************ 2622 * * 2623 * This register should be loaded before a transfer is started. The * 2624 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 2625 * address as described in Section 1.3, Figure2 and Figure3. Since * 2626 * the bottom 7 bits of the address are always taken to be zero, BTE * 2627 * transfers are always cacheline-aligned. * 2628 * * 2629 ************************************************************************/ 2630 2631 typedef union ii_ibda1_u { 2632 u64 ii_ibda1_regval; 2633 struct { 2634 u64 i_rsvd_1:7; 2635 u64 i_addr:33; 2636 u64 i_rsvd:24; 2637 } ii_ibda1_fld_s; 2638 } ii_ibda1_u_t; 2639 2640 /************************************************************************ 2641 * * 2642 * Writing to this register sets up the attributes of the transfer * 2643 * and initiates the transfer operation. Reading this register has * 2644 * the side effect of terminating any transfer in progress. Note: * 2645 * stopping a transfer midstream could have an adverse impact on the * 2646 * other BTE. If a BTE stream has to be stopped (due to error * 2647 * handling for example), both BTE streams should be stopped and * 2648 * their transfers discarded. * 2649 * * 2650 ************************************************************************/ 2651 2652 typedef union ii_ibct1_u { 2653 u64 ii_ibct1_regval; 2654 struct { 2655 u64 i_zerofill:1; 2656 u64 i_rsvd_2:3; 2657 u64 i_notify:1; 2658 u64 i_rsvd_1:3; 2659 u64 i_poison:1; 2660 u64 i_rsvd:55; 2661 } ii_ibct1_fld_s; 2662 } ii_ibct1_u_t; 2663 2664 /************************************************************************ 2665 * * 2666 * This register contains the address to which the WINV is sent. * 2667 * This address has to be cache line aligned. * 2668 * * 2669 ************************************************************************/ 2670 2671 typedef union ii_ibna1_u { 2672 u64 ii_ibna1_regval; 2673 struct { 2674 u64 i_rsvd_1:7; 2675 u64 i_addr:33; 2676 u64 i_rsvd:24; 2677 } ii_ibna1_fld_s; 2678 } ii_ibna1_u_t; 2679 2680 /************************************************************************ 2681 * * 2682 * This register contains the programmable level as well as the node * 2683 * ID and PI unit of the processor to which the interrupt will be * 2684 * sent. * 2685 * * 2686 ************************************************************************/ 2687 2688 typedef union ii_ibia1_u { 2689 u64 ii_ibia1_regval; 2690 struct { 2691 u64 i_pi_id:1; 2692 u64 i_node_id:8; 2693 u64 i_rsvd_1:7; 2694 u64 i_level:7; 2695 u64 i_rsvd:41; 2696 } ii_ibia1_fld_s; 2697 } ii_ibia1_u_t; 2698 2699 /************************************************************************ 2700 * * 2701 * This register defines the resources that feed information into * 2702 * the two performance counters located in the IO Performance * 2703 * Profiling Register. There are 17 different quantities that can be * 2704 * measured. Given these 17 different options, the two performance * 2705 * counters have 15 of them in common; menu selections 0 through 0xE * 2706 * are identical for each performance counter. As for the other two * 2707 * options, one is available from one performance counter and the * 2708 * other is available from the other performance counter. Hence, the * 2709 * II supports all 17*16=272 possible combinations of quantities to * 2710 * measure. * 2711 * * 2712 ************************************************************************/ 2713 2714 typedef union ii_ipcr_u { 2715 u64 ii_ipcr_regval; 2716 struct { 2717 u64 i_ippr0_c:4; 2718 u64 i_ippr1_c:4; 2719 u64 i_icct:8; 2720 u64 i_rsvd:48; 2721 } ii_ipcr_fld_s; 2722 } ii_ipcr_u_t; 2723 2724 /************************************************************************ 2725 * * 2726 * * 2727 * * 2728 ************************************************************************/ 2729 2730 typedef union ii_ippr_u { 2731 u64 ii_ippr_regval; 2732 struct { 2733 u64 i_ippr0:32; 2734 u64 i_ippr1:32; 2735 } ii_ippr_fld_s; 2736 } ii_ippr_u_t; 2737 2738 /************************************************************************ 2739 * * 2740 * The following defines which were not formed into structures are * 2741 * probably identical to another register, and the name of the * 2742 * register is provided against each of these registers. This * 2743 * information needs to be checked carefully * 2744 * * 2745 * IIO_ICRB1_A IIO_ICRB0_A * 2746 * IIO_ICRB1_B IIO_ICRB0_B * 2747 * IIO_ICRB1_C IIO_ICRB0_C * 2748 * IIO_ICRB1_D IIO_ICRB0_D * 2749 * IIO_ICRB1_E IIO_ICRB0_E * 2750 * IIO_ICRB2_A IIO_ICRB0_A * 2751 * IIO_ICRB2_B IIO_ICRB0_B * 2752 * IIO_ICRB2_C IIO_ICRB0_C * 2753 * IIO_ICRB2_D IIO_ICRB0_D * 2754 * IIO_ICRB2_E IIO_ICRB0_E * 2755 * IIO_ICRB3_A IIO_ICRB0_A * 2756 * IIO_ICRB3_B IIO_ICRB0_B * 2757 * IIO_ICRB3_C IIO_ICRB0_C * 2758 * IIO_ICRB3_D IIO_ICRB0_D * 2759 * IIO_ICRB3_E IIO_ICRB0_E * 2760 * IIO_ICRB4_A IIO_ICRB0_A * 2761 * IIO_ICRB4_B IIO_ICRB0_B * 2762 * IIO_ICRB4_C IIO_ICRB0_C * 2763 * IIO_ICRB4_D IIO_ICRB0_D * 2764 * IIO_ICRB4_E IIO_ICRB0_E * 2765 * IIO_ICRB5_A IIO_ICRB0_A * 2766 * IIO_ICRB5_B IIO_ICRB0_B * 2767 * IIO_ICRB5_C IIO_ICRB0_C * 2768 * IIO_ICRB5_D IIO_ICRB0_D * 2769 * IIO_ICRB5_E IIO_ICRB0_E * 2770 * IIO_ICRB6_A IIO_ICRB0_A * 2771 * IIO_ICRB6_B IIO_ICRB0_B * 2772 * IIO_ICRB6_C IIO_ICRB0_C * 2773 * IIO_ICRB6_D IIO_ICRB0_D * 2774 * IIO_ICRB6_E IIO_ICRB0_E * 2775 * IIO_ICRB7_A IIO_ICRB0_A * 2776 * IIO_ICRB7_B IIO_ICRB0_B * 2777 * IIO_ICRB7_C IIO_ICRB0_C * 2778 * IIO_ICRB7_D IIO_ICRB0_D * 2779 * IIO_ICRB7_E IIO_ICRB0_E * 2780 * IIO_ICRB8_A IIO_ICRB0_A * 2781 * IIO_ICRB8_B IIO_ICRB0_B * 2782 * IIO_ICRB8_C IIO_ICRB0_C * 2783 * IIO_ICRB8_D IIO_ICRB0_D * 2784 * IIO_ICRB8_E IIO_ICRB0_E * 2785 * IIO_ICRB9_A IIO_ICRB0_A * 2786 * IIO_ICRB9_B IIO_ICRB0_B * 2787 * IIO_ICRB9_C IIO_ICRB0_C * 2788 * IIO_ICRB9_D IIO_ICRB0_D * 2789 * IIO_ICRB9_E IIO_ICRB0_E * 2790 * IIO_ICRBA_A IIO_ICRB0_A * 2791 * IIO_ICRBA_B IIO_ICRB0_B * 2792 * IIO_ICRBA_C IIO_ICRB0_C * 2793 * IIO_ICRBA_D IIO_ICRB0_D * 2794 * IIO_ICRBA_E IIO_ICRB0_E * 2795 * IIO_ICRBB_A IIO_ICRB0_A * 2796 * IIO_ICRBB_B IIO_ICRB0_B * 2797 * IIO_ICRBB_C IIO_ICRB0_C * 2798 * IIO_ICRBB_D IIO_ICRB0_D * 2799 * IIO_ICRBB_E IIO_ICRB0_E * 2800 * IIO_ICRBC_A IIO_ICRB0_A * 2801 * IIO_ICRBC_B IIO_ICRB0_B * 2802 * IIO_ICRBC_C IIO_ICRB0_C * 2803 * IIO_ICRBC_D IIO_ICRB0_D * 2804 * IIO_ICRBC_E IIO_ICRB0_E * 2805 * IIO_ICRBD_A IIO_ICRB0_A * 2806 * IIO_ICRBD_B IIO_ICRB0_B * 2807 * IIO_ICRBD_C IIO_ICRB0_C * 2808 * IIO_ICRBD_D IIO_ICRB0_D * 2809 * IIO_ICRBD_E IIO_ICRB0_E * 2810 * IIO_ICRBE_A IIO_ICRB0_A * 2811 * IIO_ICRBE_B IIO_ICRB0_B * 2812 * IIO_ICRBE_C IIO_ICRB0_C * 2813 * IIO_ICRBE_D IIO_ICRB0_D * 2814 * IIO_ICRBE_E IIO_ICRB0_E * 2815 * * 2816 ************************************************************************/ 2817 2818 /* 2819 * Slightly friendlier names for some common registers. 2820 */ 2821 #define IIO_WIDGET IIO_WID /* Widget identification */ 2822 #define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ 2823 #define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ 2824 #define IIO_PROTECT IIO_ILAPR /* IO interface protection */ 2825 #define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ 2826 #define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ 2827 #define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ 2828 #define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ 2829 #define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ 2830 #define IIO_LLP_LOG IIO_ILLR /* LLP log */ 2831 #define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout */ 2832 #define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ 2833 #define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ 2834 #define IIO_IGFX_0 IIO_IGFX0 2835 #define IIO_IGFX_1 IIO_IGFX1 2836 #define IIO_IBCT_0 IIO_IBCT0 2837 #define IIO_IBCT_1 IIO_IBCT1 2838 #define IIO_IBLS_0 IIO_IBLS0 2839 #define IIO_IBLS_1 IIO_IBLS1 2840 #define IIO_IBSA_0 IIO_IBSA0 2841 #define IIO_IBSA_1 IIO_IBSA1 2842 #define IIO_IBDA_0 IIO_IBDA0 2843 #define IIO_IBDA_1 IIO_IBDA1 2844 #define IIO_IBNA_0 IIO_IBNA0 2845 #define IIO_IBNA_1 IIO_IBNA1 2846 #define IIO_IBIA_0 IIO_IBIA0 2847 #define IIO_IBIA_1 IIO_IBIA1 2848 #define IIO_IOPRB_0 IIO_IPRB0 2849 2850 #define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x))) 2851 #define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x))) 2852 #define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ 2853 #define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */ 2854 #define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */ 2855 2856 #define IIO_NUM_IPRBS 9 2857 2858 #define IIO_LLP_CSR_IS_UP 0x00002000 2859 #define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 2860 #define IIO_LLP_CSR_LLP_STAT_SHFT 12 2861 2862 #define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */ 2863 #define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */ 2864 2865 /* key to IIO_PROTECT_OVRRD */ 2866 #define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ 2867 2868 /* BTE register names */ 2869 #define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ 2870 #define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ 2871 #define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ 2872 #define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ 2873 #define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ 2874 #define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ 2875 #define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ 2876 #define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ 2877 2878 /* BTE register offsets from base */ 2879 #define BTEOFF_STAT 0 2880 #define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) 2881 #define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) 2882 #define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) 2883 #define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) 2884 #define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) 2885 2886 /* names used in shub diags */ 2887 #define IIO_BASE_BTE0 IIO_IBLS_0 2888 #define IIO_BASE_BTE1 IIO_IBLS_1 2889 2890 /* 2891 * Macro which takes the widget number, and returns the 2892 * IO PRB address of that widget. 2893 * value _x is expected to be a widget number in the range 2894 * 0, 8 - 0xF 2895 */ 2896 #define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ 2897 (_x) : \ 2898 (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) 2899 2900 /* GFX Flow Control Node/Widget Register */ 2901 #define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ 2902 #define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1) 2903 #define IIO_IGFX_W_NUM_SHIFT 0 2904 #define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */ 2905 #define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1) 2906 #define IIO_IGFX_PI_NUM_SHIFT 4 2907 #define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */ 2908 #define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1) 2909 #define IIO_IGFX_N_NUM_SHIFT 5 2910 #define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */ 2911 #define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1) 2912 #define IIO_IGFX_P_NUM_SHIFT 16 2913 #define IIO_IGFX_INIT(widget, pi, node, cpu) (\ 2914 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \ 2915 (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \ 2916 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ 2917 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT)) 2918 2919 /* Scratch registers (all bits available) */ 2920 #define IIO_SCRATCH_REG0 IIO_ISCR0 2921 #define IIO_SCRATCH_REG1 IIO_ISCR1 2922 #define IIO_SCRATCH_MASK 0xffffffffffffffffUL 2923 2924 #define IIO_SCRATCH_BIT0_0 0x0000000000000001UL 2925 #define IIO_SCRATCH_BIT0_1 0x0000000000000002UL 2926 #define IIO_SCRATCH_BIT0_2 0x0000000000000004UL 2927 #define IIO_SCRATCH_BIT0_3 0x0000000000000008UL 2928 #define IIO_SCRATCH_BIT0_4 0x0000000000000010UL 2929 #define IIO_SCRATCH_BIT0_5 0x0000000000000020UL 2930 #define IIO_SCRATCH_BIT0_6 0x0000000000000040UL 2931 #define IIO_SCRATCH_BIT0_7 0x0000000000000080UL 2932 #define IIO_SCRATCH_BIT0_8 0x0000000000000100UL 2933 #define IIO_SCRATCH_BIT0_9 0x0000000000000200UL 2934 #define IIO_SCRATCH_BIT0_A 0x0000000000000400UL 2935 2936 #define IIO_SCRATCH_BIT1_0 0x0000000000000001UL 2937 #define IIO_SCRATCH_BIT1_1 0x0000000000000002UL 2938 /* IO Translation Table Entries */ 2939 #define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ 2940 /* Hw manuals number them 1..7! */ 2941 /* 2942 * IIO_IMEM Register fields. 2943 */ 2944 #define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */ 2945 #define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */ 2946 #define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */ 2947 2948 /* 2949 * As a permanent workaround for a bug in the PI side of the shub, we've 2950 * redefined big window 7 as small window 0. 2951 XXX does this still apply for SN1?? 2952 */ 2953 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) 2954 2955 /* 2956 * Use the top big window as a surrogate for the first small window 2957 */ 2958 #define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW 2959 2960 #define ILCSR_WARM_RESET 0x100 2961 2962 /* 2963 * CRB manipulation macros 2964 * The CRB macros are slightly complicated, since there are up to 2965 * four registers associated with each CRB entry. 2966 */ 2967 #define IIO_NUM_CRBS 15 /* Number of CRBs */ 2968 #define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ 2969 #define IIO_ICRB_OFFSET 8 2970 #define IIO_ICRB_0 IIO_ICRB0_A 2971 #define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ 2972 /* XXX - This is now tuneable: 2973 #define IIO_FIRST_PC_ENTRY 12 2974 */ 2975 2976 #define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))) 2977 #define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)) 2978 #define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)) 2979 #define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)) 2980 #define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)) 2981 2982 #define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) 2983 2984 /* 2985 * values for "ecode" field 2986 */ 2987 #define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ 2988 #define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ 2989 #define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access 2990 * e.g. WINV to a Read only line. */ 2991 #define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ 2992 #define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ 2993 #define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ 2994 #define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ 2995 #define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ 2996 2997 /* 2998 * Values for field imsgtype 2999 */ 3000 #define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ 3001 #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ 3002 #define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */ 3003 #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ 3004 3005 /* 3006 * values for field initiator. 3007 */ 3008 #define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ 3009 #define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ 3010 #define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */ 3011 #define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ 3012 #define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ 3013 3014 /* 3015 * Number of credits Hub widget has while sending req/response to 3016 * xbow. 3017 * Value of 3 is required by Xbow 1.1 3018 * We may be able to increase this to 4 with Xbow 1.2. 3019 */ 3020 #define HUBII_XBOW_CREDIT 3 3021 #define HUBII_XBOW_REV2_CREDIT 4 3022 3023 /* 3024 * Number of credits that xtalk devices should use when communicating 3025 * with a SHub (depth of SHub's queue). 3026 */ 3027 #define HUB_CREDIT 4 3028 3029 /* 3030 * Some IIO_PRB fields 3031 */ 3032 #define IIO_PRB_MULTI_ERR (1LL << 63) 3033 #define IIO_PRB_SPUR_RD (1LL << 51) 3034 #define IIO_PRB_SPUR_WR (1LL << 50) 3035 #define IIO_PRB_RD_TO (1LL << 49) 3036 #define IIO_PRB_ERROR (1LL << 48) 3037 3038 /************************************************************************* 3039 3040 Some of the IIO field masks and shifts are defined here. 3041 This is in order to maintain compatibility in SN0 and SN1 code 3042 3043 **************************************************************************/ 3044 3045 /* 3046 * ICMR register fields 3047 * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not 3048 * present in SHub) 3049 */ 3050 3051 #define IIO_ICMR_CRB_VLD_SHFT 20 3052 #define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) 3053 3054 #define IIO_ICMR_FC_CNT_SHFT 16 3055 #define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) 3056 3057 #define IIO_ICMR_C_CNT_SHFT 4 3058 #define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) 3059 3060 #define IIO_ICMR_PRECISE (1UL << 52) 3061 #define IIO_ICMR_CLR_RPPD (1UL << 13) 3062 #define IIO_ICMR_CLR_RQPD (1UL << 12) 3063 3064 /* 3065 * IIO PIO Deallocation register field masks : (IIO_IPDR) 3066 XXX present but not needed in bedrock? See the manual. 3067 */ 3068 #define IIO_IPDR_PND (1 << 4) 3069 3070 /* 3071 * IIO CRB deallocation register field masks: (IIO_ICDR) 3072 */ 3073 #define IIO_ICDR_PND (1 << 4) 3074 3075 /* 3076 * IO BTE Length/Status (IIO_IBLS) register bit field definitions 3077 */ 3078 #define IBLS_BUSY (0x1UL << 20) 3079 #define IBLS_ERROR_SHFT 16 3080 #define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT) 3081 #define IBLS_LENGTH_MASK 0xffff 3082 3083 /* 3084 * IO BTE Control/Terminate register (IBCT) register bit field definitions 3085 */ 3086 #define IBCT_POISON (0x1UL << 8) 3087 #define IBCT_NOTIFY (0x1UL << 4) 3088 #define IBCT_ZFIL_MODE (0x1UL << 0) 3089 3090 /* 3091 * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2) 3092 */ 3093 #define IIEPH1_VALID (1UL << 44) 3094 #define IIEPH1_OVERRUN (1UL << 40) 3095 #define IIEPH1_ERR_TYPE_SHFT 32 3096 #define IIEPH1_ERR_TYPE_MASK 0xf 3097 #define IIEPH1_SOURCE_SHFT 20 3098 #define IIEPH1_SOURCE_MASK 11 3099 #define IIEPH1_SUPPL_SHFT 8 3100 #define IIEPH1_SUPPL_MASK 11 3101 #define IIEPH1_CMD_SHFT 0 3102 #define IIEPH1_CMD_MASK 7 3103 3104 #define IIEPH2_TAIL (1UL << 40) 3105 #define IIEPH2_ADDRESS_SHFT 0 3106 #define IIEPH2_ADDRESS_MASK 38 3107 3108 #define IIEPH1_ERR_SHORT_REQ 2 3109 #define IIEPH1_ERR_SHORT_REPLY 3 3110 #define IIEPH1_ERR_LONG_REQ 4 3111 #define IIEPH1_ERR_LONG_REPLY 5 3112 3113 /* 3114 * IO Error Clear register bit field definitions 3115 */ 3116 #define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */ 3117 #define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */ 3118 #define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */ 3119 #define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */ 3120 #define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */ 3121 #define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */ 3122 #define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */ 3123 #define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */ 3124 #define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */ 3125 #define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */ 3126 #define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */ 3127 #define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */ 3128 #define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */ 3129 #define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */ 3130 #define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */ 3131 3132 /* 3133 * IIO CRB control register Fields: IIO_ICCR 3134 */ 3135 #define IIO_ICCR_PENDING 0x10000 3136 #define IIO_ICCR_CMD_MASK 0xFF 3137 #define IIO_ICCR_CMD_SHFT 7 3138 #define IIO_ICCR_CMD_NOP 0x0 /* No Op */ 3139 #define IIO_ICCR_CMD_WAKE 0x100 /* Reactivate CRB entry and process */ 3140 #define IIO_ICCR_CMD_TIMEOUT 0x200 /* Make CRB timeout & mark invalid */ 3141 #define IIO_ICCR_CMD_EJECT 0x400 /* Contents of entry written to memory 3142 * via a WB 3143 */ 3144 #define IIO_ICCR_CMD_FLUSH 0x800 3145 3146 /* 3147 * 3148 * CRB Register description. 3149 * 3150 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3151 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3152 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3153 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3154 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3155 * 3156 * Many of the fields in CRB are status bits used by hardware 3157 * for implementation of the protocol. It's very dangerous to 3158 * mess around with the CRB registers. 3159 * 3160 * It's OK to read the CRB registers and try to make sense out of the 3161 * fields in CRB. 3162 * 3163 * Updating CRB requires all activities in Hub IIO to be quiesced. 3164 * otherwise, a write to CRB could corrupt other CRB entries. 3165 * CRBs are here only as a back door peek to shub IIO's status. 3166 * Quiescing implies no dmas no PIOs 3167 * either directly from the cpu or from sn0net. 3168 * this is not something that can be done easily. So, AVOID updating 3169 * CRBs. 3170 */ 3171 3172 /* 3173 * Easy access macros for CRBs, all 5 registers (A-E) 3174 */ 3175 typedef ii_icrb0_a_u_t icrba_t; 3176 #define a_sidn ii_icrb0_a_fld_s.ia_sidn 3177 #define a_tnum ii_icrb0_a_fld_s.ia_tnum 3178 #define a_addr ii_icrb0_a_fld_s.ia_addr 3179 #define a_valid ii_icrb0_a_fld_s.ia_vld 3180 #define a_iow ii_icrb0_a_fld_s.ia_iow 3181 #define a_regvalue ii_icrb0_a_regval 3182 3183 typedef ii_icrb0_b_u_t icrbb_t; 3184 #define b_use_old ii_icrb0_b_fld_s.ib_use_old 3185 #define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype 3186 #define b_imsg ii_icrb0_b_fld_s.ib_imsg 3187 #define b_initiator ii_icrb0_b_fld_s.ib_init 3188 #define b_exc ii_icrb0_b_fld_s.ib_exc 3189 #define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt 3190 #define b_resp ii_icrb0_b_fld_s.ib_resp 3191 #define b_ack ii_icrb0_b_fld_s.ib_ack 3192 #define b_hold ii_icrb0_b_fld_s.ib_hold 3193 #define b_wb ii_icrb0_b_fld_s.ib_wb 3194 #define b_intvn ii_icrb0_b_fld_s.ib_intvn 3195 #define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib 3196 #define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr 3197 #define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0 3198 #define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1 3199 #define b_error ii_icrb0_b_fld_s.ib_error 3200 #define b_ecode ii_icrb0_b_fld_s.ib_errcode 3201 #define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce 3202 #define b_mark ii_icrb0_b_fld_s.ib_mark 3203 #define b_xerr ii_icrb0_b_fld_s.ib_xt_err 3204 #define b_regvalue ii_icrb0_b_regval 3205 3206 typedef ii_icrb0_c_u_t icrbc_t; 3207 #define c_suppl ii_icrb0_c_fld_s.ic_suppl 3208 #define c_barrop ii_icrb0_c_fld_s.ic_bo 3209 #define c_doresp ii_icrb0_c_fld_s.ic_resprqd 3210 #define c_gbr ii_icrb0_c_fld_s.ic_gbr 3211 #define c_btenum ii_icrb0_c_fld_s.ic_bte_num 3212 #define c_cohtrans ii_icrb0_c_fld_s.ic_ct 3213 #define c_xtsize ii_icrb0_c_fld_s.ic_size 3214 #define c_source ii_icrb0_c_fld_s.ic_source 3215 #define c_regvalue ii_icrb0_c_regval 3216 3217 typedef ii_icrb0_d_u_t icrbd_t; 3218 #define d_sleep ii_icrb0_d_fld_s.id_sleep 3219 #define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt 3220 #define d_pripsc ii_icrb0_d_fld_s.id_pr_psc 3221 #define d_bteop ii_icrb0_d_fld_s.id_bte_op 3222 #define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */ 3223 #define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */ 3224 #define d_regvalue ii_icrb0_d_regval 3225 3226 typedef ii_icrb0_e_u_t icrbe_t; 3227 #define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld 3228 #define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld 3229 #define icrbe_context ii_icrb0_e_fld_s.ie_context 3230 #define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout 3231 #define e_regvalue ii_icrb0_e_regval 3232 3233 /* Number of widgets supported by shub */ 3234 #define HUB_NUM_WIDGET 9 3235 #define HUB_WIDGET_ID_MIN 0x8 3236 #define HUB_WIDGET_ID_MAX 0xf 3237 3238 #define HUB_WIDGET_PART_NUM 0xc120 3239 #define MAX_HUBS_PER_XBOW 2 3240 3241 /* A few more #defines for backwards compatibility */ 3242 #define iprb_t ii_iprb0_u_t 3243 #define iprb_regval ii_iprb0_regval 3244 #define iprb_mult_err ii_iprb0_fld_s.i_mult_err 3245 #define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd 3246 #define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr 3247 #define iprb_rd_to ii_iprb0_fld_s.i_rd_to 3248 #define iprb_ovflow ii_iprb0_fld_s.i_of_cnt 3249 #define iprb_error ii_iprb0_fld_s.i_error 3250 #define iprb_ff ii_iprb0_fld_s.i_f 3251 #define iprb_mode ii_iprb0_fld_s.i_m 3252 #define iprb_bnakctr ii_iprb0_fld_s.i_nb 3253 #define iprb_anakctr ii_iprb0_fld_s.i_na 3254 #define iprb_xtalkctr ii_iprb0_fld_s.i_c 3255 3256 #define LNK_STAT_WORKING 0x2 /* LLP is working */ 3257 3258 #define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ 3259 #define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ 3260 #define IIO_WSTAT_TXRETRY_MASK 0x7F /* should be 0xFF?? */ 3261 #define IIO_WSTAT_TXRETRY_SHFT 16 3262 #define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ 3263 IIO_WSTAT_TXRETRY_MASK) 3264 3265 /* Number of II perf. counters we can multiplex at once */ 3266 3267 #define IO_PERF_SETS 32 3268 3269 /* Bit for the widget in inbound access register */ 3270 #define IIO_IIWA_WIDGET(_w) ((u64)(1ULL << _w)) 3271 /* Bit for the widget in outbound access register */ 3272 #define IIO_IOWA_WIDGET(_w) ((u64)(1ULL << _w)) 3273 3274 /* NOTE: The following define assumes that we are going to get 3275 * widget numbers from 8 thru F and the device numbers within 3276 * widget from 0 thru 7. 3277 */ 3278 #define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d)))) 3279 3280 /* IO Interrupt Destination Register */ 3281 #define IIO_IIDSR_SENT_SHIFT 28 3282 #define IIO_IIDSR_SENT_MASK 0x30000000 3283 #define IIO_IIDSR_ENB_SHIFT 24 3284 #define IIO_IIDSR_ENB_MASK 0x01000000 3285 #define IIO_IIDSR_NODE_SHIFT 9 3286 #define IIO_IIDSR_NODE_MASK 0x000ff700 3287 #define IIO_IIDSR_PI_ID_SHIFT 8 3288 #define IIO_IIDSR_PI_ID_MASK 0x00000100 3289 #define IIO_IIDSR_LVL_SHIFT 0 3290 #define IIO_IIDSR_LVL_MASK 0x000000ff 3291 3292 /* Xtalk timeout threshold register (IIO_IXTT) */ 3293 #define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ 3294 #define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT) 3295 #define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ 3296 #define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT) 3297 #define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ 3298 #define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT) 3299 3300 /* 3301 * The IO LLP control status register and widget control register 3302 */ 3303 3304 typedef union hubii_wcr_u { 3305 u64 wcr_reg_value; 3306 struct { 3307 u64 wcr_widget_id:4, /* LLP crossbar credit */ 3308 wcr_tag_mode:1, /* Tag mode */ 3309 wcr_rsvd1:8, /* Reserved */ 3310 wcr_xbar_crd:3, /* LLP crossbar credit */ 3311 wcr_f_bad_pkt:1, /* Force bad llp pkt enable */ 3312 wcr_dir_con:1, /* widget direct connect */ 3313 wcr_e_thresh:5, /* elasticity threshold */ 3314 wcr_rsvd:41; /* unused */ 3315 } wcr_fields_s; 3316 } hubii_wcr_t; 3317 3318 #define iwcr_dir_con wcr_fields_s.wcr_dir_con 3319 3320 /* The structures below are defined to extract and modify the ii 3321 performance registers */ 3322 3323 /* io_perf_sel allows the caller to specify what tests will be 3324 performed */ 3325 3326 typedef union io_perf_sel { 3327 u64 perf_sel_reg; 3328 struct { 3329 u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48; 3330 } perf_sel_bits; 3331 } io_perf_sel_t; 3332 3333 /* io_perf_cnt is to extract the count from the shub registers. Due to 3334 hardware problems there is only one counter, not two. */ 3335 3336 typedef union io_perf_cnt { 3337 u64 perf_cnt; 3338 struct { 3339 u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32; 3340 } perf_cnt_bits; 3341 3342 } io_perf_cnt_t; 3343 3344 typedef union iprte_a { 3345 u64 entry; 3346 struct { 3347 u64 i_rsvd_1:3; 3348 u64 i_addr:38; 3349 u64 i_init:3; 3350 u64 i_source:8; 3351 u64 i_rsvd:2; 3352 u64 i_widget:4; 3353 u64 i_to_cnt:5; 3354 u64 i_vld:1; 3355 } iprte_fields; 3356 } iprte_a_t; 3357 3358 #endif /* _ASM_IA64_SN_SHUBIO_H */ 3359