Searched refs:gpt_clk (Results 1 – 10 of 10) sorted by relevance
/linux-3.4.99/arch/arm/plat-spear/ |
D | time.c | 66 static struct clk *gpt_clk; variable 82 tick_rate = clk_get_rate(gpt_clk); in spear_clocksource_init() 118 period = clk_get_rate(gpt_clk) / HZ; in clockevent_set_mode() 185 tick_rate = clk_get_rate(gpt_clk); in spear_clockevent_init() 216 gpt_clk = clk_get_sys("gpt0", NULL); in spear_setup_timer() 217 if (!gpt_clk) { in spear_setup_timer() 222 ret = clk_enable(gpt_clk); in spear_setup_timer() 234 clk_put(gpt_clk); in spear_setup_timer()
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/linux-3.4.99/arch/arm/mach-spear6xx/ |
D | spear6xx.c | 67 struct clk *gpt_clk, *pclk; in spear6xx_timer_init() local 70 gpt_clk = clk_get_sys("gpt0", NULL); in spear6xx_timer_init() 71 if (IS_ERR(gpt_clk)) { in spear6xx_timer_init() 84 clk_set_parent(gpt_clk, pclk); in spear6xx_timer_init() 85 clk_put(gpt_clk); in spear6xx_timer_init()
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/linux-3.4.99/arch/arm/mach-spear3xx/ |
D | spear3xx.c | 512 struct clk *gpt_clk, *pclk; in spear3xx_timer_init() local 515 gpt_clk = clk_get_sys("gpt0", NULL); in spear3xx_timer_init() 516 if (IS_ERR(gpt_clk)) { in spear3xx_timer_init() 529 clk_set_parent(gpt_clk, pclk); in spear3xx_timer_init() 530 clk_put(gpt_clk); in spear3xx_timer_init()
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/linux-3.4.99/arch/arm/mach-imx/ |
D | clock-imx1.c | 526 static struct clk gpt_clk = { variable 589 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 632 mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), in mx1_clocks_init()
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D | clock-imx35.c | 361 DEFINE_CLOCK(gpt_clk, 0, MX35_CCM_CGR1, 8, get_rate_ipg, NULL); 453 _REGISTER_CLOCK("gpt.0", NULL, gpt_clk) 531 mxc_timer_init(&gpt_clk, in mx35_clocks_init()
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D | clock-imx21.c | 693 static struct clk gpt_clk[] = { variable 1169 _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0]) 1170 _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1]) 1171 _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2]) 1236 mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), in mx21_clocks_init()
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D | clock-imx25.c | 218 DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL); 343 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); in mx25_clocks_init()
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D | clock-imx31.c | 475 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk); 531 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 611 clk_enable(&gpt_clk); in mx31_clocks_init()
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D | clock-mx51-mx53.c | 1280 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, 1454 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 1508 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 1595 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), in mx51_clocks_init() 1632 mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), in mx53_clocks_init()
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D | clock-imx6q.c | 1832 DEF_CLK(gpt_clk, CCGR1, CG10, &ipg_perclk, &gpt_serial_clk); 2108 mxc_timer_init(&gpt_clk, base, irq); in mx6q_clocks_init()
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